/* SPDX-License-Identifier: GPL-2.0+ */
#define PLL_REF_CTRL_REG 0x00000000 //PLL_REF Control Register
  #define PLL_REF_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_REF_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_REF_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_REF_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_REF_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_REF_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_REF_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_REF_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_REF_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_REF_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_REF_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_REF_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_REF_CTRL_REG_LOCK_OFFSET 28
  #define PLL_REF_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_REF_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_REF_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
    #define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_DISABLE (0b0)
    #define PLL_REF_CTRL_REG_PLL_OUTPUT_GATE_ENABLE (0b1)
  #define PLL_REF_CTRL_REG_PLL_REG_EN_OFFSET 24
  #define PLL_REF_CTRL_REG_PLL_REG_EN_CLEAR_MASK (0x01000000)
    #define PLL_REF_CTRL_REG_PLL_REG_EN_DISABLE (0b0)
    #define PLL_REF_CTRL_REG_PLL_REG_EN_ENABLE (0b1)
  #define PLL_REF_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 16
  #define PLL_REF_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x007f0000)
  #define PLL_REF_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_REF_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_REF_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_REF_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_REF_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_REF_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_REF_LOCK_CTRL_REG 0x00000004 //PLL_REF Lock Control Register
  #define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_OFFSET 4
  #define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_STAT_PENDING (0b1)
  #define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_OFFSET 0
  #define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_REF_LOCK_CTRL_REG_PLL_REF_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_REF_BIAS_REG 0x00000010 //PLL_REF Bias Register
  #define PLL_REF_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_REF_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_DDR_CTRL_REG 0x00000020 //PLL_DDR Control Register
  #define PLL_DDR_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_DDR_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_DDR_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_DDR_CTRL_REG_LOCK_OFFSET 28
  #define PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_DDR_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
    #define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE (0b0)
    #define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE (0b1)
  #define PLL_DDR_CTRL_REG_PLL_FREF_SEL_OFFSET 24
  #define PLL_DDR_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)
    #define PLL_DDR_CTRL_REG_PLL_FREF_SEL_HOSC (0b0)
    #define PLL_DDR_CTRL_REG_PLL_FREF_SEL_REFPLL (0b1)
  #define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20
  #define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000)
  #define PLL_DDR_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_DDR_LOCK_CTRL_REG 0x00000024 //PLL_DDR Lock Control Register
  #define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_OFFSET 4
  #define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_STAT_PENDING (0b1)
  #define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_OFFSET 0
  #define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_DDR_LOCK_CTRL_REG_PLL_DDR_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_DDR_PAT0_CTRL_REG 0x00000028 //PLL_DDR Pattern0 Control Register
  #define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
  #define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
    #define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW (0b00)
    #define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT (0b01)
    #define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT (0b10)
    #define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT (0b11)
  #define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
  #define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19
  #define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)
    #define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_UP (0b0)
    #define PLL_DDR_PAT0_CTRL_REG_SDM_DIRECTION_DOWN (0b1)
  #define PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
    #define PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ (0b00)
    #define PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ (0b01)
    #define PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ (0b10)
    #define PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ (0b11)
  #define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_DDR_PAT1_CTRL_REG 0x0000002c //PLL_DDR Pattern1 Control Register
  #define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31
  #define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)
    #define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_DISABLE (0b0)
    #define PLL_DDR_PAT1_CTRL_REG_PLL_PI_EN_ENABLE (0b1)
  #define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28
  #define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)
    // #define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b000)
    // #define PLL_DDR_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b001)
  #define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27
  #define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)
    #define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE (0b0)
    #define PLL_DDR_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE (0b1)
  #define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26
  #define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)
    #define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY (0b0)
    #define PLL_DDR_PAT1_CTRL_REG_SDM_BUSY_BUSY (0b1)
  #define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25
  #define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)
    #define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_DISABLE (0b0)
    #define PLL_DDR_PAT1_CTRL_REG_SMOOTH_EN_ENABLE (0b1)
  #define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
  #define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
  #define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_DDR_BIAS_REG 0x00000030 //PLL_DDR Bias Register
  #define PLL_DDR_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_PERI0_CTRL_REG 0x000000a0 //PLL_PERI0 Control Register
  #define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_PERI0_CTRL_REG_LOCK_OFFSET 28
  #define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27
  #define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000)
    #define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE (0b0)
    #define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE (0b1)
  #define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26
  #define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000)
    #define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE (0b0)
    #define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE (0b1)
  #define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_OFFSET 25
  #define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_CLEAR_MASK (0x02000000)
    #define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_DISABLE (0b0)
    #define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_GATE_ENABLE (0b1)
  #define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_OFFSET 24
  #define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)
    #define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_HOSC (0b0)
    #define PLL_PERI0_CTRL_REG_PLL_FREF_SEL_REFPLL (0b1)
  #define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20
  #define PLL_PERI0_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000)
  #define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16
  #define PLL_PERI0_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000)
  #define PLL_PERI0_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_DIV_OFFSET 2
  #define PLL_PERI0_CTRL_REG_PLL_OUTPUT2_DIV_CLEAR_MASK (0x0000001c)
  #define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_PERI0_LOCK_CTRL_REG 0x000000a4 //PLL_PERI0 Lock Control Register
  #define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_OFFSET 4
  #define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_STAT_PENDING (0b1)
  #define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_OFFSET 0
  #define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_PERI0_LOCK_CTRL_REG_PLL_PERI0_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_PERI0_PAT0_CTRL_REG 0x000000a8 //PLL_PERI0 Pattern0 Control Register
  #define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
  #define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
    #define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW (0b00)
    #define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT (0b01)
    #define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT (0b10)
    #define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT (0b11)
  #define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
  #define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19
  #define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)
    #define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_UP (0b0)
    #define PLL_PERI0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN (0b1)
  #define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
    #define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ (0b00)
    #define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ (0b01)
    #define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ (0b10)
    #define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ (0b11)
  #define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_PERI0_PAT1_CTRL_REG 0x000000ac //PLL_PERI0 Pattern1 Control Register
  #define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31
  #define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)
    #define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE (0b0)
    #define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE (0b1)
  #define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28
  #define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)
    // #define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b000)
    // #define PLL_PERI0_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b001)
  #define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27
  #define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)
    #define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE (0b0)
    #define PLL_PERI0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE (0b1)
  #define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26
  #define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)
    #define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY (0b0)
    #define PLL_PERI0_PAT1_CTRL_REG_SDM_BUSY_BUSY (0b1)
  #define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25
  #define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)
    #define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE (0b0)
    #define PLL_PERI0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE (0b1)
  #define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
  #define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
  #define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_PERI0_BIAS_REG 0x000000b0 //PLL_PERI0 Bias register
  #define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_PERI1_CTRL_REG 0x000000c0 //PLL_PERI1 Control Register
  #define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_PERI1_CTRL_REG_LOCK_OFFSET 28
  #define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27
  #define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000)
    #define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE (0b0)
    #define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE (0b1)
  #define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26
  #define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000)
    #define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE (0b0)
    #define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE (0b1)
  #define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_OFFSET 25
  #define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_CLEAR_MASK (0x02000000)
    #define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_DISABLE (0b0)
    #define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_GATE_ENABLE (0b1)
  #define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_OFFSET 24
  #define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)
    #define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_HOSC (0b0)
    #define PLL_PERI1_CTRL_REG_PLL_FREF_SEL_REFPLL (0b1)
  #define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20
  #define PLL_PERI1_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000)
  #define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16
  #define PLL_PERI1_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000)
  #define PLL_PERI1_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_DIV_OFFSET 2
  #define PLL_PERI1_CTRL_REG_PLL_OUTPUT2_DIV_CLEAR_MASK (0x0000001c)
  #define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_PERI1_LOCK_CTRL_REG 0x000000c4 //PLL_PERI1 Lock Control Register
  #define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_OFFSET 4
  #define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_STAT_PENDING (0b1)
  #define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_OFFSET 0
  #define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_PERI1_LOCK_CTRL_REG_PLL_PERI1_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_PERI1_PAT0_CTRL_REG 0x000000c8 //PLL_PERI1 Pattern0 Control Register
  #define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
  #define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
    #define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW (0b00)
    #define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT (0b01)
    #define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT (0b10)
    #define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT (0b11)
  #define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
  #define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19
  #define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)
    #define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_UP (0b0)
    #define PLL_PERI1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN (0b1)
  #define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
    #define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ (0b00)
    #define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ (0b01)
    #define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ (0b10)
    #define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ (0b11)
  #define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_PERI1_PAT1_CTRL_REG 0x000000cc //PLL_PERI1 Pattern1 Control Register
  #define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31
  #define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)
    #define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE (0b0)
    #define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE (0b1)
  #define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28
  #define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)
    // #define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b000)
    // #define PLL_PERI1_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b001)
  #define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27
  #define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)
    #define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE (0b0)
    #define PLL_PERI1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE (0b1)
  #define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26
  #define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)
    #define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY (0b0)
    #define PLL_PERI1_PAT1_CTRL_REG_SDM_BUSY_BUSY (0b1)
  #define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25
  #define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)
    #define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE (0b0)
    #define PLL_PERI1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE (0b1)
  #define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
  #define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
  #define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_PERI1_BIAS_REG 0x000000d0 //PLL_PERI1 Bias Register
  #define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_GPU0_CTRL_REG 0x000000e0 //PLL_GPU0 Control Register
  #define PLL_GPU0_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_GPU0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_GPU0_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_GPU0_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_GPU0_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_GPU0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_GPU0_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_GPU0_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_GPU0_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_GPU0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_GPU0_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_GPU0_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_GPU0_CTRL_REG_LOCK_OFFSET 28
  #define PLL_GPU0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_GPU0_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_GPU0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
    #define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE (0b0)
    #define PLL_GPU0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE (0b1)
  #define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_OFFSET 24
  #define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)
    #define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_HOSC (0b0)
    #define PLL_GPU0_CTRL_REG_PLL_FREF_SEL_REFPLL (0b1)
  #define PLL_GPU0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20
  #define PLL_GPU0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000)
  #define PLL_GPU0_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_GPU0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_GPU0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_GPU0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_GPU0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_GPU0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_GPU0_LOCK_CTRL_REG 0x000000e4 //PLL_GPU0 Lock Control Register
  #define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_OFFSET 4
  #define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_STAT_PENDING (0b1)
  #define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_OFFSET 0
  #define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_GPU0_LOCK_CTRL_REG_PLL_GPU0_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_GPU0_PAT0_CTRL_REG 0x000000e8 //PLL_GPU0 Pattern0 Control Register
  #define PLL_GPU0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_GPU0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
  #define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
    #define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW (0b00)
    #define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT (0b01)
    #define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT (0b10)
    #define PLL_GPU0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT (0b11)
  #define PLL_GPU0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_GPU0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
  #define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19
  #define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)
    #define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_UP (0b0)
    #define PLL_GPU0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN (0b1)
  #define PLL_GPU0_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_GPU0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
    #define PLL_GPU0_PAT0_CTRL_REG_FREQ_31_5KHZ (0b00)
    #define PLL_GPU0_PAT0_CTRL_REG_FREQ_32KHZ (0b01)
    #define PLL_GPU0_PAT0_CTRL_REG_FREQ_32_5KHZ (0b10)
    #define PLL_GPU0_PAT0_CTRL_REG_FREQ_33KHZ (0b11)
  #define PLL_GPU0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_GPU0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_GPU0_PAT1_CTRL_REG 0x000000ec //PLL_GPU0 Pattern1 Control Register
  #define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31
  #define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)
    #define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE (0b0)
    #define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE (0b1)
  #define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28
  #define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)
    // #define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b000)
    // #define PLL_GPU0_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b001)
  #define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27
  #define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)
    #define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE (0b0)
    #define PLL_GPU0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE (0b1)
  #define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26
  #define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)
    #define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY (0b0)
    #define PLL_GPU0_PAT1_CTRL_REG_SDM_BUSY_BUSY (0b1)
  #define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25
  #define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)
    #define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE (0b0)
    #define PLL_GPU0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE (0b1)
  #define PLL_GPU0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_GPU0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
  #define PLL_GPU0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_GPU0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
  #define PLL_GPU0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_GPU0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_GPU0_BIAS_REG 0x000000f0 //PLL_GPU0 Bias Register
  #define PLL_GPU0_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_GPU0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_VIDEO0_CTRL_REG 0x00000120 //PLL_VIDEO0 Control Register
  #define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET 28
  #define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27
  #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000)
    #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE (0b0)
    #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE (0b1)
  #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26
  #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000)
    #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE (0b0)
    #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE (0b1)
  #define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_OFFSET 24
  #define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)
    #define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_HOSC (0b0)
    #define PLL_VIDEO0_CTRL_REG_PLL_FREF_SEL_REFPLL (0b1)
  #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20
  #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000)
  #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16
  #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000)
  #define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_VIDEO0_LOCK_CTRL_REG 0x00000124 //PLL_VIDEO0 Lock Control Register
  #define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_OFFSET 4
  #define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_STAT_PENDING (0b1)
  #define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_OFFSET 0
  #define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_VIDEO0_LOCK_CTRL_REG_PLL_VIDEO0_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_VIDEO0_PAT0_CTRL_REG 0x00000128 //PLL_VIDEO0 Pattern0 Control Register
  #define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
  #define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
    #define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW (0b00)
    #define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT (0b01)
    #define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT (0b10)
    #define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT (0b11)
  #define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
  #define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19
  #define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)
    #define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_UP (0b0)
    #define PLL_VIDEO0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN (0b1)
  #define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
    #define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ (0b00)
    #define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ (0b01)
    #define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ (0b10)
    #define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ (0b11)
  #define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_VIDEO0_PAT1_CTRL_REG 0x0000012c //PLL_VIDEO0 Pattern1 Control Register
  #define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31
  #define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)
    #define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE (0b0)
    #define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE (0b1)
  #define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28
  #define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)
    // #define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b000)
    // #define PLL_VIDEO0_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b001)
  #define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27
  #define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)
    #define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE (0b0)
    #define PLL_VIDEO0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE (0b1)
  #define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26
  #define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)
    #define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY (0b0)
    #define PLL_VIDEO0_PAT1_CTRL_REG_SDM_BUSY_BUSY (0b1)
  #define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25
  #define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)
    #define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE (0b0)
    #define PLL_VIDEO0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE (0b1)
  #define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
  #define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
  #define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_VIDEO0_BIAS_REG 0x00000130 //PLL_VIDEO0 Bias Register
  #define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_VIDEO1_CTRL_REG 0x00000140 //PLL_VIDEO1 Control Register
  #define PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_VIDEO1_CTRL_REG_LOCK_OFFSET 28
  #define PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27
  #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000)
    #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE (0b0)
    #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE (0b1)
  #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26
  #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000)
    #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE (0b0)
    #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE (0b1)
  #define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_OFFSET 24
  #define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)
    #define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_HOSC (0b0)
    #define PLL_VIDEO1_CTRL_REG_PLL_FREF_SEL_REFPLL (0b1)
  #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20
  #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000)
  #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16
  #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000)
  #define PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_VIDEO1_LOCK_CTRL_REG 0x00000144 //PLL_VIDEO1 Lock Control Register
  #define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_OFFSET 4
  #define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_STAT_PENDING (0b1)
  #define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_OFFSET 0
  #define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_VIDEO1_LOCK_CTRL_REG_PLL_VIDEO1_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_VIDEO1_PAT0_CTRL_REG 0x00000148 //PLL_VIDEO1 Pattern0 Control Register
  #define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
  #define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
    #define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW (0b00)
    #define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT (0b01)
    #define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT (0b10)
    #define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT (0b11)
  #define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
  #define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19
  #define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)
    #define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_UP (0b0)
    #define PLL_VIDEO1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN (0b1)
  #define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
    #define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ (0b00)
    #define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ (0b01)
    #define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ (0b10)
    #define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ (0b11)
  #define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_VIDEO1_PAT1_CTRL_REG 0x0000014c //PLL_VIDEO1 Pattern1 Control Register
  #define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31
  #define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)
    #define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE (0b0)
    #define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE (0b1)
  #define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28
  #define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)
    // #define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b000)
    // #define PLL_VIDEO1_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b001)
  #define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27
  #define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)
    #define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE (0b0)
    #define PLL_VIDEO1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE (0b1)
  #define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26
  #define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)
    #define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY (0b0)
    #define PLL_VIDEO1_PAT1_CTRL_REG_SDM_BUSY_BUSY (0b1)
  #define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25
  #define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)
    #define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE (0b0)
    #define PLL_VIDEO1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE (0b1)
  #define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
  #define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
  #define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_VIDEO1_BIAS_REG 0x00000150 //PLL_VIDEO1 Bias Register
  #define PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_VIDEO2_CTRL_REG 0x00000160 //PLL_VIDEO2 Control Register
  #define PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_VIDEO2_CTRL_REG_LOCK_OFFSET 28
  #define PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27
  #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000)
    #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE (0b0)
    #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE (0b1)
  #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26
  #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000)
    #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE (0b0)
    #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE (0b1)
  #define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_OFFSET 24
  #define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)
    #define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_HOSC (0b0)
    #define PLL_VIDEO2_CTRL_REG_PLL_FREF_SEL_REFPLL (0b1)
  #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20
  #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000)
  #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16
  #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000)
  #define PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_VIDEO2_LOCK_CTRL_REG 0x00000164 //PLL_VIDEO2 Lock Control Register
  #define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_OFFSET 4
  #define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_STAT_PENDING (0b1)
  #define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_OFFSET 0
  #define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_VIDEO2_LOCK_CTRL_REG_PLL_VIDEO2_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_VIDEO2_PAT0_CTRL_REG 0x00000168 //PLL_VIDEO2 Pattern0 Control Register
  #define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
  #define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
    #define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW (0b00)
    #define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT (0b01)
    #define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT (0b10)
    #define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT (0b11)
  #define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
  #define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19
  #define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)
    #define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_UP (0b0)
    #define PLL_VIDEO2_PAT0_CTRL_REG_SDM_DIRECTION_DOWN (0b1)
  #define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
    #define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ (0b00)
    #define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ (0b01)
    #define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ (0b10)
    #define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ (0b11)
  #define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_VIDEO2_PAT1_CTRL_REG 0x0000016c //PLL_VIDEO2 Pattern1 Control Register
  #define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31
  #define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)
    #define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_DISABLE (0b0)
    #define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_EN_ENABLE (0b1)
  #define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28
  #define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)
    // #define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b000)
    // #define PLL_VIDEO2_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b001)
  #define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27
  #define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)
    #define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE (0b0)
    #define PLL_VIDEO2_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE (0b1)
  #define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26
  #define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)
    #define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY (0b0)
    #define PLL_VIDEO2_PAT1_CTRL_REG_SDM_BUSY_BUSY (0b1)
  #define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25
  #define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)
    #define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_DISABLE (0b0)
    #define PLL_VIDEO2_PAT1_CTRL_REG_SMOOTH_EN_ENABLE (0b1)
  #define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
  #define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
  #define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_VIDEO2_BIAS_REG 0x00000170 //PLL_VIDEO2 Bias Register
  #define PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_VIDEO3_CTRL_REG 0x00000180 //PLL_VIDEO3 Control Register
  #define PLL_VIDEO3_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_VIDEO3_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_VIDEO3_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_VIDEO3_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_VIDEO3_CTRL_REG_LOCK_OFFSET 28
  #define PLL_VIDEO3_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_VIDEO3_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_VIDEO3_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27
  #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000)
    #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE (0b0)
    #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE (0b1)
  #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26
  #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000)
    #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE (0b0)
    #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE (0b1)
  #define PLL_VIDEO3_CTRL_REG_PLL_FREF_SEL_OFFSET 24
  #define PLL_VIDEO3_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)
    #define PLL_VIDEO3_CTRL_REG_PLL_FREF_SEL_HOSC (0b0)
    #define PLL_VIDEO3_CTRL_REG_PLL_FREF_SEL_REFPLL (0b1)
  #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20
  #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000)
  #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16
  #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000)
  #define PLL_VIDEO3_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_VIDEO3_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_VIDEO3_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_VIDEO3_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_VIDEO3_LOCK_CTRL_REG 0x00000184 //PLL_VIDEO3 Lock Control Register
  #define PLL_VIDEO3_LOCK_CTRL_REG_PLL_VIDEO3_UNLOCK_STAT_OFFSET 4
  #define PLL_VIDEO3_LOCK_CTRL_REG_PLL_VIDEO3_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_VIDEO3_LOCK_CTRL_REG_PLL_VIDEO3_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_VIDEO3_LOCK_CTRL_REG_PLL_VIDEO3_UNLOCK_STAT_PENDING (0b1)
  #define PLL_VIDEO3_LOCK_CTRL_REG_PLL_VIDEO3_UNLOCK_IRQEN_OFFSET 0
  #define PLL_VIDEO3_LOCK_CTRL_REG_PLL_VIDEO3_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_VIDEO3_LOCK_CTRL_REG_PLL_VIDEO3_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_VIDEO3_LOCK_CTRL_REG_PLL_VIDEO3_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_VIDEO3_PAT0_CTRL_REG 0x00000188 //PLL_VIDEO3 Pattern0 Control Register
  #define PLL_VIDEO3_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_VIDEO3_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
  #define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
    #define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW (0b00)
    #define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT (0b01)
    #define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT (0b10)
    #define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT (0b11)
  #define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
  #define PLL_VIDEO3_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19
  #define PLL_VIDEO3_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)
    #define PLL_VIDEO3_PAT0_CTRL_REG_SDM_DIRECTION_UP (0b0)
    #define PLL_VIDEO3_PAT0_CTRL_REG_SDM_DIRECTION_DOWN (0b1)
  #define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
    #define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_31_5KHZ (0b00)
    #define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_32KHZ (0b01)
    #define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_32_5KHZ (0b10)
    #define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_33KHZ (0b11)
  #define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_VIDEO3_PAT1_CTRL_REG 0x0000018c //PLL_VIDEO3 Pattern1 Control Register
  #define PLL_VIDEO3_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31
  #define PLL_VIDEO3_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)
    #define PLL_VIDEO3_PAT1_CTRL_REG_PLL_PI_EN_DISABLE (0b0)
    #define PLL_VIDEO3_PAT1_CTRL_REG_PLL_PI_EN_ENABLE (0b1)
  #define PLL_VIDEO3_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28
  #define PLL_VIDEO3_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)
    // #define PLL_VIDEO3_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b000)
    // #define PLL_VIDEO3_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b001)
  #define PLL_VIDEO3_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27
  #define PLL_VIDEO3_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)
    #define PLL_VIDEO3_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE (0b0)
    #define PLL_VIDEO3_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE (0b1)
  #define PLL_VIDEO3_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26
  #define PLL_VIDEO3_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)
    #define PLL_VIDEO3_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY (0b0)
    #define PLL_VIDEO3_PAT1_CTRL_REG_SDM_BUSY_BUSY (0b1)
  #define PLL_VIDEO3_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25
  #define PLL_VIDEO3_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)
    #define PLL_VIDEO3_PAT1_CTRL_REG_SMOOTH_EN_DISABLE (0b0)
    #define PLL_VIDEO3_PAT1_CTRL_REG_SMOOTH_EN_ENABLE (0b1)
  #define PLL_VIDEO3_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_VIDEO3_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
  #define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
  #define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_VIDEO3_BIAS_REG 0x00000190 //PLL_VIDEO3 Bias Register
  #define PLL_VIDEO3_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_VIDEO3_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_VE0_CTRL_REG 0x00000220 //PLL_VE0 Control Register
  #define PLL_VE0_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_VE0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_VE0_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_VE0_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_VE0_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_VE0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_VE0_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_VE0_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_VE0_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_VE0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_VE0_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_VE0_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_VE0_CTRL_REG_LOCK_OFFSET 28
  #define PLL_VE0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_VE0_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_VE0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
    #define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE (0b0)
    #define PLL_VE0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE (0b1)
  #define PLL_VE0_CTRL_REG_PLL_FREF_SEL_OFFSET 24
  #define PLL_VE0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)
    #define PLL_VE0_CTRL_REG_PLL_FREF_SEL_HOSC (0b0)
    #define PLL_VE0_CTRL_REG_PLL_FREF_SEL_REFPLL (0b1)
  #define PLL_VE0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20
  #define PLL_VE0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000)
  #define PLL_VE0_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_VE0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_VE0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_VE0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_VE0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_VE0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_VE0_LOCK_CTRL_REG 0x00000224 //PLL_VE0 Lock Control Register
  #define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_OFFSET 4
  #define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_STAT_PENDING (0b1)
  #define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_OFFSET 0
  #define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_VE0_LOCK_CTRL_REG_PLL_VE0_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_VE0_PAT0_CTRL_REG 0x00000228 //PLL_VE0 Pattern0 Control Register
  #define PLL_VE0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_VE0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
  #define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
    #define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW (0b00)
    #define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT (0b01)
    #define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT (0b10)
    #define PLL_VE0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT (0b11)
  #define PLL_VE0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_VE0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
  #define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19
  #define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)
    #define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_UP (0b0)
    #define PLL_VE0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN (0b1)
  #define PLL_VE0_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_VE0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
    #define PLL_VE0_PAT0_CTRL_REG_FREQ_31_5KHZ (0b00)
    #define PLL_VE0_PAT0_CTRL_REG_FREQ_32KHZ (0b01)
    #define PLL_VE0_PAT0_CTRL_REG_FREQ_32_5KHZ (0b10)
    #define PLL_VE0_PAT0_CTRL_REG_FREQ_33KHZ (0b11)
  #define PLL_VE0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_VE0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_VE0_PAT1_CTRL_REG 0x0000022c //PLL_VE0 Pattern1 Control Register
  #define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31
  #define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)
    #define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE (0b0)
    #define PLL_VE0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE (0b1)
  #define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28
  #define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)
    // #define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b000)
    // #define PLL_VE0_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b001)
  #define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27
  #define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)
    #define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE (0b0)
    #define PLL_VE0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE (0b1)
  #define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26
  #define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)
    #define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY (0b0)
    #define PLL_VE0_PAT1_CTRL_REG_SDM_BUSY_BUSY (0b1)
  #define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25
  #define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)
    #define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE (0b0)
    #define PLL_VE0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE (0b1)
  #define PLL_VE0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_VE0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
  #define PLL_VE0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_VE0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
  #define PLL_VE0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_VE0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_VE0_BIAS_REG 0x00000230 //PLL_VE0 Bias Register
  #define PLL_VE0_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_VE0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_VE1_CTRL_REG 0x00000240 //PLL_VE1 Control Register
  #define PLL_VE1_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_VE1_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_VE1_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_VE1_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_VE1_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_VE1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_VE1_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_VE1_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_VE1_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_VE1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_VE1_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_VE1_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_VE1_CTRL_REG_LOCK_OFFSET 28
  #define PLL_VE1_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_VE1_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_VE1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
    #define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE (0b0)
    #define PLL_VE1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE (0b1)
  #define PLL_VE1_CTRL_REG_PLL_FREF_SEL_OFFSET 24
  #define PLL_VE1_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)
    #define PLL_VE1_CTRL_REG_PLL_FREF_SEL_HOSC (0b0)
    #define PLL_VE1_CTRL_REG_PLL_FREF_SEL_REFPLL (0b1)
  #define PLL_VE1_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20
  #define PLL_VE1_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000)
  #define PLL_VE1_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_VE1_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_VE1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_VE1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_VE1_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_VE1_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_VE1_LOCK_CTRL_REG 0x00000244 //PLL_VE1 Lock Control Register
  #define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_OFFSET 4
  #define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_STAT_PENDING (0b1)
  #define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_OFFSET 0
  #define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_VE1_LOCK_CTRL_REG_PLL_VE1_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_VE1_PAT0_CTRL_REG 0x00000248 //PLL_VE1 Pattern0 Control Register
  #define PLL_VE1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_VE1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
  #define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
    #define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW (0b00)
    #define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT (0b01)
    #define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT (0b10)
    #define PLL_VE1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT (0b11)
  #define PLL_VE1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_VE1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
  #define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19
  #define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)
    #define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_UP (0b0)
    #define PLL_VE1_PAT0_CTRL_REG_SDM_DIRECTION_DOWN (0b1)
  #define PLL_VE1_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_VE1_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
    #define PLL_VE1_PAT0_CTRL_REG_FREQ_31_5KHZ (0b00)
    #define PLL_VE1_PAT0_CTRL_REG_FREQ_32KHZ (0b01)
    #define PLL_VE1_PAT0_CTRL_REG_FREQ_32_5KHZ (0b10)
    #define PLL_VE1_PAT0_CTRL_REG_FREQ_33KHZ (0b11)
  #define PLL_VE1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_VE1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_VE1_PAT1_CTRL_REG 0x0000024c //PLL_VE1 Pattern1 Control Register
  #define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31
  #define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)
    #define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_DISABLE (0b0)
    #define PLL_VE1_PAT1_CTRL_REG_PLL_PI_EN_ENABLE (0b1)
  #define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28
  #define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)
    // #define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b000)
    // #define PLL_VE1_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b001)
  #define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27
  #define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)
    #define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE (0b0)
    #define PLL_VE1_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE (0b1)
  #define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26
  #define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)
    #define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY (0b0)
    #define PLL_VE1_PAT1_CTRL_REG_SDM_BUSY_BUSY (0b1)
  #define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25
  #define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)
    #define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_DISABLE (0b0)
    #define PLL_VE1_PAT1_CTRL_REG_SMOOTH_EN_ENABLE (0b1)
  #define PLL_VE1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_VE1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
  #define PLL_VE1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_VE1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
  #define PLL_VE1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_VE1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_VE1_BIAS_REG 0x00000250 //PLL_VE1 Bias Register
  #define PLL_VE1_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_VE1_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_AUDIO0_CTRL_REG 0x00000260 //PLL_AUDIO0 Control Register
  #define PLL_AUDIO0_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_AUDIO0_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_AUDIO0_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_AUDIO0_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_AUDIO0_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_AUDIO0_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_AUDIO0_CTRL_REG_LOCK_OFFSET 28
  #define PLL_AUDIO0_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_AUDIO0_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_AUDIO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
    #define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE (0b0)
    #define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE (0b1)
  #define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_OFFSET 24
  #define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)
    #define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_HOSC (0b0)
    #define PLL_AUDIO0_CTRL_REG_PLL_FREF_SEL_REFPLL (0b1)
  #define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 16
  #define PLL_AUDIO0_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x007f0000)
  #define PLL_AUDIO0_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_AUDIO0_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_AUDIO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_AUDIO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_AUDIO0_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_AUDIO0_LOCK_CTRL_REG 0x00000264 //PLL_AUDIO0 Lock Control Register
  #define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_OFFSET 4
  #define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_STAT_PENDING (0b1)
  #define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_OFFSET 0
  #define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_AUDIO0_LOCK_CTRL_REG_PLL_AUDIO0_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_AUDIO0_PAT0_CTRL_REG 0x00000268 //PLL_AUDIO0 Pattern0 Control Register
  #define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_AUDIO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
  #define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
    #define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW (0b00)
    #define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT (0b01)
    #define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT (0b10)
    #define PLL_AUDIO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT (0b11)
  #define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
  #define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19
  #define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)
    #define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_UP (0b0)
    #define PLL_AUDIO0_PAT0_CTRL_REG_SDM_DIRECTION_DOWN (0b1)
  #define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
    #define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_31_5KHZ (0b00)
    #define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32KHZ (0b01)
    #define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_32_5KHZ (0b10)
    #define PLL_AUDIO0_PAT0_CTRL_REG_FREQ_33KHZ (0b11)
  #define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_AUDIO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_AUDIO0_PAT1_CTRL_REG 0x0000026c //PLL_AUDIO0 Pattern1 Control Register
  #define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31
  #define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)
    #define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_DISABLE (0b0)
    #define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_EN_ENABLE (0b1)
  #define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28
  #define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)
    // #define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b000)
    // #define PLL_AUDIO0_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b001)
  #define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27
  #define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)
    #define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE (0b0)
    #define PLL_AUDIO0_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE (0b1)
  #define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26
  #define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)
    #define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY (0b0)
    #define PLL_AUDIO0_PAT1_CTRL_REG_SDM_BUSY_BUSY (0b1)
  #define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25
  #define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)
    #define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_DISABLE (0b0)
    #define PLL_AUDIO0_PAT1_CTRL_REG_SMOOTH_EN_ENABLE (0b1)
  #define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_AUDIO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
  #define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
  #define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_AUDIO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_AUDIO0_BIAS_REG 0x00000270 //PLL_AUDIO0 Bias Register
  #define PLL_AUDIO0_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_AUDIO0_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_NPU_CTRL_REG 0x000002a0 //PLL_NPU Control Register
  #define PLL_NPU_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_NPU_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_NPU_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_NPU_CTRL_REG_LOCK_OFFSET 28
  #define PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_NPU_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
    #define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE (0b0)
    #define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE (0b1)
  #define PLL_NPU_CTRL_REG_PLL_FREF_SEL_OFFSET 24
  #define PLL_NPU_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)
    #define PLL_NPU_CTRL_REG_PLL_FREF_SEL_HOSC (0b0)
    #define PLL_NPU_CTRL_REG_PLL_FREF_SEL_REFPLL (0b1)
  #define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20
  #define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000)
  #define PLL_NPU_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_NPU_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_NPU_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_NPU_LOCK_CTRL_REG 0x000002a4 //PLL_NPU Lock Control Register
  #define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_OFFSET 4
  #define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_STAT_PENDING (0b1)
  #define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_OFFSET 0
  #define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_NPU_LOCK_CTRL_REG_PLL_NPU_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_NPU_PAT0_CTRL_REG 0x000002a8 //PLL_NPU Pattern0 Control Register
  #define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
  #define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
    #define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW (0b00)
    #define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT (0b01)
    #define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT (0b10)
    #define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT (0b11)
  #define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
  #define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19
  #define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)
    #define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_UP (0b0)
    #define PLL_NPU_PAT0_CTRL_REG_SDM_DIRECTION_DOWN (0b1)
  #define PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
    #define PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ (0b00)
    #define PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ (0b01)
    #define PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ (0b10)
    #define PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ (0b11)
  #define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_NPU_PAT1_CTRL_REG 0x000002ac //PLL_NPU Pattern1 Control Register
  #define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31
  #define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)
    #define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_DISABLE (0b0)
    #define PLL_NPU_PAT1_CTRL_REG_PLL_PI_EN_ENABLE (0b1)
  #define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28
  #define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)
    // #define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b000)
    // #define PLL_NPU_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b001)
  #define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27
  #define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)
    #define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE (0b0)
    #define PLL_NPU_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE (0b1)
  #define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26
  #define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)
    #define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY (0b0)
    #define PLL_NPU_PAT1_CTRL_REG_SDM_BUSY_BUSY (0b1)
  #define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25
  #define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)
    #define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_DISABLE (0b0)
    #define PLL_NPU_PAT1_CTRL_REG_SMOOTH_EN_ENABLE (0b1)
  #define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
  #define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
  #define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_NPU_BIAS_REG 0x000002b0 //PLL_NPU Bias Register
  #define PLL_NPU_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_DE_CTRL_REG 0x000002e0 //PLL_DE Control Register
  #define PLL_DE_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_DE_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_DE_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_DE_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_DE_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_DE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_DE_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_DE_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_DE_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_DE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_DE_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_DE_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_DE_CTRL_REG_LOCK_OFFSET 28
  #define PLL_DE_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_DE_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_DE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_OFFSET 27
  #define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_CLEAR_MASK (0x08000000)
    #define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_DISABLE (0b0)
    #define PLL_DE_CTRL_REG_PLL_OUTPUT0_GATE_ENABLE (0b1)
  #define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_OFFSET 26
  #define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_CLEAR_MASK (0x04000000)
    #define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_DISABLE (0b0)
    #define PLL_DE_CTRL_REG_PLL_OUTPUT1_GATE_ENABLE (0b1)
  #define PLL_DE_CTRL_REG_PLL_FREF_SEL_OFFSET 24
  #define PLL_DE_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)
    #define PLL_DE_CTRL_REG_PLL_FREF_SEL_HOSC (0b0)
    #define PLL_DE_CTRL_REG_PLL_FREF_SEL_REFPLL (0b1)
  #define PLL_DE_CTRL_REG_PLL_OUTPUT0_DIV_OFFSET 20
  #define PLL_DE_CTRL_REG_PLL_OUTPUT0_DIV_CLEAR_MASK (0x00700000)
  #define PLL_DE_CTRL_REG_PLL_OUTPUT1_DIV_OFFSET 16
  #define PLL_DE_CTRL_REG_PLL_OUTPUT1_DIV_CLEAR_MASK (0x00070000)
  #define PLL_DE_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_DE_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_DE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_DE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_DE_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_DE_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_DE_LOCK_CTRL_REG 0x000002e4 //PLL_DE Lock Control Register
  #define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_OFFSET 4
  #define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_STAT_PENDING (0b1)
  #define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_OFFSET 0
  #define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_DE_LOCK_CTRL_REG_PLL_DE_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_DE_PAT0_CTRL_REG 0x000002e8 //PLL_DE Pattern0 Control Register
  #define PLL_DE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_DE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
  #define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
    #define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW (0b00)
    #define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT (0b01)
    #define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT (0b10)
    #define PLL_DE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT (0b11)
  #define PLL_DE_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_DE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
  #define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19
  #define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)
    #define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_UP (0b0)
    #define PLL_DE_PAT0_CTRL_REG_SDM_DIRECTION_DOWN (0b1)
  #define PLL_DE_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_DE_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
    #define PLL_DE_PAT0_CTRL_REG_FREQ_31_5KHZ (0b00)
    #define PLL_DE_PAT0_CTRL_REG_FREQ_32KHZ (0b01)
    #define PLL_DE_PAT0_CTRL_REG_FREQ_32_5KHZ (0b10)
    #define PLL_DE_PAT0_CTRL_REG_FREQ_33KHZ (0b11)
  #define PLL_DE_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_DE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_DE_PAT1_CTRL_REG 0x000002ec //PLL_DE Pattern1 Control Register
  #define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31
  #define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)
    #define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_DISABLE (0b0)
    #define PLL_DE_PAT1_CTRL_REG_PLL_PI_EN_ENABLE (0b1)
  #define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28
  #define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)
    // #define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b000)
    // #define PLL_DE_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b001)
  #define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27
  #define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)
    #define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE (0b0)
    #define PLL_DE_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE (0b1)
  #define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26
  #define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)
    #define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY (0b0)
    #define PLL_DE_PAT1_CTRL_REG_SDM_BUSY_BUSY (0b1)
  #define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25
  #define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)
    #define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_DISABLE (0b0)
    #define PLL_DE_PAT1_CTRL_REG_SMOOTH_EN_ENABLE (0b1)
  #define PLL_DE_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_DE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
  #define PLL_DE_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_DE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
  #define PLL_DE_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_DE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_DE_BIAS_REG 0x000002f0 //PLL_DE Bias Register
  #define PLL_DE_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_DE_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_CCI_CTRL_REG 0x00000320 //PLL_CCI Control Register
  #define PLL_CCI_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_CCI_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
    #define PLL_CCI_CTRL_REG_PLL_EN_DISABLE (0b0)
    #define PLL_CCI_CTRL_REG_PLL_EN_ENABLE (0b1)
  #define PLL_CCI_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_CCI_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
    #define PLL_CCI_CTRL_REG_PLL_LDO_EN_DISABLE (0b0)
    #define PLL_CCI_CTRL_REG_PLL_LDO_EN_ENABLE (0b1)
  #define PLL_CCI_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_CCI_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
    #define PLL_CCI_CTRL_REG_LOCK_ENABLE_DISABLE (0b0)
    #define PLL_CCI_CTRL_REG_LOCK_ENABLE_ENABLE (0b1)
  #define PLL_CCI_CTRL_REG_LOCK_OFFSET 28
  #define PLL_CCI_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
    #define PLL_CCI_CTRL_REG_LOCK_UNLOCKED (0b0)
    #define PLL_CCI_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE (0b1)
  #define PLL_CCI_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_CCI_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
    #define PLL_CCI_CTRL_REG_PLL_OUTPUT_GATE_DISABLE (0b0)
    #define PLL_CCI_CTRL_REG_PLL_OUTPUT_GATE_ENABLE (0b1)
  #define PLL_CCI_CTRL_REG_PLL_FREF_SEL_OFFSET 24
  #define PLL_CCI_CTRL_REG_PLL_FREF_SEL_CLEAR_MASK (0x01000000)
    #define PLL_CCI_CTRL_REG_PLL_FREF_SEL_HOSC (0b0)
    #define PLL_CCI_CTRL_REG_PLL_FREF_SEL_REFPLL (0b1)
  #define PLL_CCI_CTRL_REG_PLL_OUTPUT_DIV_OFFSET 20
  #define PLL_CCI_CTRL_REG_PLL_OUTPUT_DIV_CLEAR_MASK (0x00700000)
  #define PLL_CCI_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_CCI_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
  #define PLL_CCI_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_CCI_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
    #define PLL_CCI_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES (0b00)
    #define PLL_CCI_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES (0b01)
    #define PLL_CCI_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES (0b10)
  #define PLL_CCI_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_CCI_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
    #define PLL_CCI_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES (0b0)
    #define PLL_CCI_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES (0b1)
  #define PLL_CCI_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
  #define PLL_CCI_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000002)

#define PLL_CCI_LOCK_CTRL_REG 0x00000324 //PLL_CCI Lock Control Register
  #define PLL_CCI_LOCK_CTRL_REG_PLL_CCI_UNLOCK_STAT_OFFSET 4
  #define PLL_CCI_LOCK_CTRL_REG_PLL_CCI_UNLOCK_STAT_CLEAR_MASK (0x00000010)
    #define PLL_CCI_LOCK_CTRL_REG_PLL_CCI_UNLOCK_STAT_NO_EFFECT (0b0)
    #define PLL_CCI_LOCK_CTRL_REG_PLL_CCI_UNLOCK_STAT_PENDING (0b1)
  #define PLL_CCI_LOCK_CTRL_REG_PLL_CCI_UNLOCK_IRQEN_OFFSET 0
  #define PLL_CCI_LOCK_CTRL_REG_PLL_CCI_UNLOCK_IRQEN_CLEAR_MASK (0x00000001)
    #define PLL_CCI_LOCK_CTRL_REG_PLL_CCI_UNLOCK_IRQEN_DISABLE (0b0)
    #define PLL_CCI_LOCK_CTRL_REG_PLL_CCI_UNLOCK_IRQEN_ENABLE (0b1)

#define PLL_CCI_PAT0_CTRL_REG 0x00000328 //PLL_CCI Pattern0 Control Register
  #define PLL_CCI_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_CCI_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
  #define PLL_CCI_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_CCI_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0x60000000)
    #define PLL_CCI_PAT0_CTRL_REG_SPR_FREQ_MODE_PULSE_SWALLOW (0b00)
    #define PLL_CCI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT (0b01)
    #define PLL_CCI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_2BIT (0b10)
    #define PLL_CCI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_3BIT (0b11)
  #define PLL_CCI_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_CCI_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x1ff00000)
  #define PLL_CCI_PAT0_CTRL_REG_SDM_DIRECTION_OFFSET 19
  #define PLL_CCI_PAT0_CTRL_REG_SDM_DIRECTION_CLEAR_MASK (0x00080000)
    #define PLL_CCI_PAT0_CTRL_REG_SDM_DIRECTION_UP (0b0)
    #define PLL_CCI_PAT0_CTRL_REG_SDM_DIRECTION_DOWN (0b1)
  #define PLL_CCI_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_CCI_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
    #define PLL_CCI_PAT0_CTRL_REG_FREQ_31_5KHZ (0b00)
    #define PLL_CCI_PAT0_CTRL_REG_FREQ_32KHZ (0b01)
    #define PLL_CCI_PAT0_CTRL_REG_FREQ_32_5KHZ (0b10)
    #define PLL_CCI_PAT0_CTRL_REG_FREQ_33KHZ (0b11)
  #define PLL_CCI_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_CCI_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_CCI_PAT1_CTRL_REG 0x0000032c //PLL_CCI Pattern1 Control Register
  #define PLL_CCI_PAT1_CTRL_REG_PLL_PI_EN_OFFSET 31
  #define PLL_CCI_PAT1_CTRL_REG_PLL_PI_EN_CLEAR_MASK (0x80000000)
    #define PLL_CCI_PAT1_CTRL_REG_PLL_PI_EN_DISABLE (0b0)
    #define PLL_CCI_PAT1_CTRL_REG_PLL_PI_EN_ENABLE (0b1)
  #define PLL_CCI_PAT1_CTRL_REG_PLL_PI_CFG_OFFSET 28
  #define PLL_CCI_PAT1_CTRL_REG_PLL_PI_CFG_CLEAR_MASK (0x70000000)
    // #define PLL_CCI_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b000)
    // #define PLL_CCI_PAT1_CTRL_REG_PLL_PI_CFG_XXX (0b001)
  #define PLL_CCI_PAT1_CTRL_REG_PLL_SDM_EN_OFFSET 27
  #define PLL_CCI_PAT1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x08000000)
    #define PLL_CCI_PAT1_CTRL_REG_PLL_SDM_EN_DISABLE (0b0)
    #define PLL_CCI_PAT1_CTRL_REG_PLL_SDM_EN_ENABLE (0b1)
  #define PLL_CCI_PAT1_CTRL_REG_SDM_BUSY_OFFSET 26
  #define PLL_CCI_PAT1_CTRL_REG_SDM_BUSY_CLEAR_MASK (0x04000000)
    #define PLL_CCI_PAT1_CTRL_REG_SDM_BUSY_NOT_BUSY (0b0)
    #define PLL_CCI_PAT1_CTRL_REG_SDM_BUSY_BUSY (0b1)
  #define PLL_CCI_PAT1_CTRL_REG_SMOOTH_EN_OFFSET 25
  #define PLL_CCI_PAT1_CTRL_REG_SMOOTH_EN_CLEAR_MASK (0x02000000)
    #define PLL_CCI_PAT1_CTRL_REG_SMOOTH_EN_DISABLE (0b0)
    #define PLL_CCI_PAT1_CTRL_REG_SMOOTH_EN_ENABLE (0b1)
  #define PLL_CCI_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_CCI_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
  #define PLL_CCI_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_CCI_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
  #define PLL_CCI_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_CCI_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_CCI_BIAS_REG 0x00000330 //PLL_CCI Bias Register
  #define PLL_CCI_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_CCI_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define AHB_CLK_REG 0x00000500 //AHB Clock Register
  #define AHB_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x03000000)
    #define AHB_CLK_REG_CLK_SRC_SEL_HOSC (0b00)
    #define AHB_CLK_REG_CLK_SRC_SEL_CLK32K (0b01)
    #define AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b10)
    #define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS (0b11)
  #define AHB_CLK_REG_FACTOR_M_OFFSET 0
  #define AHB_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define APB0_CLK_REG 0x00000510 //APB0 Clock Register
  #define APB0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x03000000)
    #define APB0_CLK_REG_CLK_SRC_SEL_HOSC (0b00)
    #define APB0_CLK_REG_CLK_SRC_SEL_CLK32K (0b01)
    #define APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b10)
    #define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS (0b11)
  #define APB0_CLK_REG_FACTOR_M_OFFSET 0
  #define APB0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define APB1_CLK_REG 0x00000518 //APB1 Clock Register
  #define APB1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x03000000)
    #define APB1_CLK_REG_CLK_SRC_SEL_HOSC (0b00)
    #define APB1_CLK_REG_CLK_SRC_SEL_CLK32K (0b01)
    #define APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b10)
    #define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS (0b11)
  #define APB1_CLK_REG_FACTOR_M_OFFSET 0
  #define APB1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define APB_UART_CLK_REG 0x00000538 //APB_UART Clock Register
  #define APB_UART_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define APB_UART_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define APB_UART_CLK_REG_CLK_SRC_SEL_HOSC (0b000)
    #define APB_UART_CLK_REG_CLK_SRC_SEL_CLK32K (0b001)
    #define APB_UART_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b010)
    #define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS (0b011)
    #define APB_UART_CLK_REG_CLK_SRC_SEL_PERI0_480M_BUS (0b100)
  #define APB_UART_CLK_REG_FACTOR_M_OFFSET 0
  #define APB_UART_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define TRACE_CLK_REG 0x00000540 //TRACE Clock Register
  #define TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET 31
  #define TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON (0b1)
  #define TRACE_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TRACE_CLK_REG_CLK_SRC_SEL_HOSC (0b000)
    #define TRACE_CLK_REG_CLK_SRC_SEL_CLK32K (0b001)
    #define TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b010)
    #define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b011)
    #define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_400M (0b100)
  #define TRACE_CLK_REG_FACTOR_M_OFFSET 0
  #define TRACE_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define CCI_CLK_REG 0x00000548 //CCI Clock Register
  #define CCI_CLK_REG_CCI_CLK_GATING_OFFSET 31
  #define CCI_CLK_REG_CCI_CLK_GATING_CLEAR_MASK (0x80000000)
    #define CCI_CLK_REG_CCI_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define CCI_CLK_REG_CCI_CLK_GATING_CLOCK_IS_ON (0b1)
  #define CCI_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define CCI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define CCI_CLK_REG_CLK_SRC_SEL_HOSC (0b000)
    #define CCI_CLK_REG_CLK_SRC_SEL_CCIPLL (0b001)
    #define CCI_CLK_REG_CLK_SRC_SEL_PERI0_800M (0b010)
    #define CCI_CLK_REG_CLK_SRC_SEL_PERI0_600M (0b011)
    #define CCI_CLK_REG_CLK_SRC_SEL_DEPLL3X (0b100)
    #define CCI_CLK_REG_CLK_SRC_SEL_DDRPLL (0b101)
  #define CCI_CLK_REG_FACTOR_M_OFFSET 0
  #define CCI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define GIC_CLK_REG 0x00000560 //GIC Clock Register
  #define GIC_CLK_REG_GIC_CLK_GATING_OFFSET 31
  #define GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK (0x80000000)
    #define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON (0b1)
  #define GIC_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x03000000)
    #define GIC_CLK_REG_CLK_SRC_SEL_HOSC (0b000)
    #define GIC_CLK_REG_CLK_SRC_SEL_CLK32K (0b001)
    #define GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M (0b010)
    #define GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M (0b011)
  #define GIC_CLK_REG_FACTOR_M_OFFSET 0
  #define GIC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define NSI_CLK_REG 0x00000580 //NSI Clock Register
  #define NSI_CLK_REG_NSI_CLK_GATING_OFFSET 31
  #define NSI_CLK_REG_NSI_CLK_GATING_CLEAR_MASK (0x80000000)
    #define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define NSI_CLK_REG_NSI_CLK_GATING_CLOCK_IS_ON (0b1)
  #define NSI_CLK_REG_NSI_RST_OFFSET 30
  #define NSI_CLK_REG_NSI_RST_CLEAR_MASK (0x40000000)
    #define NSI_CLK_REG_NSI_RST_ASSERT (0b0)
    #define NSI_CLK_REG_NSI_RST_DE_ASSERT (0b1)
  #define NSI_CLK_REG_NSI_DFS_EN_OFFSET 28
  #define NSI_CLK_REG_NSI_DFS_EN_CLEAR_MASK (0x10000000)
    #define NSI_CLK_REG_NSI_DFS_EN_DISABLE (0b0)
    #define NSI_CLK_REG_NSI_DFS_EN_ENABLE (0b1)
  #define NSI_CLK_REG_NSI_UPD_OFFSET 27
  #define NSI_CLK_REG_NSI_UPD_CLEAR_MASK (0x08000000)
    #define NSI_CLK_REG_NSI_UPD_INVALID (0b0)
    #define NSI_CLK_REG_NSI_UPD_VALID (0b1)
  #define NSI_CLK_REG_NSI_CLK_SEL_OFFSET 24
  #define NSI_CLK_REG_NSI_CLK_SEL_CLEAR_MASK (0x07000000)
    #define NSI_CLK_REG_NSI_CLK_SEL_DDRPLL (0b000)
    #define NSI_CLK_REG_NSI_CLK_SEL_PERI0_800M (0b001)
    #define NSI_CLK_REG_NSI_CLK_SEL_PERI0_600M (0b010)
    #define NSI_CLK_REG_NSI_CLK_SEL_CCIPLL (0b011)
    #define NSI_CLK_REG_NSI_CLK_SEL_DEPLL3X (0b100)
    #define NSI_CLK_REG_NSI_CLK_SEL_NPUPLL (0b101)
  #define NSI_CLK_REG_NSI_DIV1_OFFSET 0
  #define NSI_CLK_REG_NSI_DIV1_CLEAR_MASK (0x0000001f)

#define NSI_BGR_REG 0x00000584 //NSI Bus Gating Reset Register
  #define NSI_BGR_REG_NSI_CFG_RST_OFFSET 16
  #define NSI_BGR_REG_NSI_CFG_RST_CLEAR_MASK (0x00010000)
    #define NSI_BGR_REG_NSI_CFG_RST_ASSERT (0b0)
    #define NSI_BGR_REG_NSI_CFG_RST_DE_ASSERT (0b1)
  #define NSI_BGR_REG_NSI_CFG_GATING_OFFSET 0
  #define NSI_BGR_REG_NSI_CFG_GATING_CLEAR_MASK (0x00000001)
    #define NSI_BGR_REG_NSI_CFG_GATING_MASK (0x0)
    #define NSI_BGR_REG_NSI_CFG_GATING_PASS (0b1)

#define MBUS_CLK_REG 0x00000588 //MBUS Clock Register
  #define MBUS_CLK_REG_MBUS_CLK_GATING_OFFSET 31
  #define MBUS_CLK_REG_MBUS_CLK_GATING_CLEAR_MASK (0x80000000)
    #define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define MBUS_CLK_REG_MBUS_CLK_GATING_CLOCK_IS_ON (0b1)
  #define MBUS_CLK_REG_MBUS_RST_OFFSET 30
  #define MBUS_CLK_REG_MBUS_RST_CLEAR_MASK (0x40000000)
    #define MBUS_CLK_REG_MBUS_RST_ASSERT (0b0)
    #define MBUS_CLK_REG_MBUS_RST_DE_ASSERT (0b1)
  #define MBUS_CLK_REG_MBUS_DFS_EN_OFFSET 28
  #define MBUS_CLK_REG_MBUS_DFS_EN_CLEAR_MASK (0x10000000)
    #define MBUS_CLK_REG_MBUS_DFS_EN_DISABLE (0b0)
    #define MBUS_CLK_REG_MBUS_DFS_EN_ENABLE (0b1)
  #define MBUS_CLK_REG_MBUS_UPD_OFFSET 27
  #define MBUS_CLK_REG_MBUS_UPD_CLEAR_MASK (0x08000000)
    #define MBUS_CLK_REG_MBUS_UPD_INVALID (0b0)
    #define MBUS_CLK_REG_MBUS_UPD_VALID (0b1)
  #define MBUS_CLK_REG_MBUS_CLK_SEL_OFFSET 24
  #define MBUS_CLK_REG_MBUS_CLK_SEL_CLEAR_MASK (0x07000000)
    #define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_600M (0b000)
    #define MBUS_CLK_REG_MBUS_CLK_SEL_DDRPLL (0b001)
    #define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_480M (0b010)
    #define MBUS_CLK_REG_MBUS_CLK_SEL_PERI0_400M (0b011)
    #define MBUS_CLK_REG_MBUS_CLK_SEL_CCIPLL (0b100)
    #define MBUS_CLK_REG_MBUS_CLK_SEL_NPUPLL (0b101)
  #define MBUS_CLK_REG_MBUS_DIV1_OFFSET 0
  #define MBUS_CLK_REG_MBUS_DIV1_CLEAR_MASK (0x0000001f)

#define SMMU_BGR_REG 0x0000058c //SMMU Bus Gating Reset Register
  #define SMMU_BGR_REG_SMMU_TCU_RST_OFFSET 31
  #define SMMU_BGR_REG_SMMU_TCU_RST_CLEAR_MASK (0x80000000)
    #define SMMU_BGR_REG_SMMU_TCU_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_TCU_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_GPU1_RST_OFFSET 30
  #define SMMU_BGR_REG_SMMU_GPU1_RST_CLEAR_MASK (0x40000000)
    #define SMMU_BGR_REG_SMMU_GPU1_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_GPU1_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_AIPU_RST_OFFSET 29
  #define SMMU_BGR_REG_SMMU_AIPU_RST_CLEAR_MASK (0x20000000)
    #define SMMU_BGR_REG_SMMU_AIPU_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_AIPU_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_NPU_RST_OFFSET 28
  #define SMMU_BGR_REG_SMMU_NPU_RST_CLEAR_MASK (0x10000000)
    #define SMMU_BGR_REG_SMMU_NPU_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_NPU_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_GPU0_RST_OFFSET 27
  #define SMMU_BGR_REG_SMMU_GPU0_RST_CLEAR_MASK (0x08000000)
    #define SMMU_BGR_REG_SMMU_GPU0_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_GPU0_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_PCIE1_RST_OFFSET 25
  #define SMMU_BGR_REG_SMMU_PCIE1_RST_CLEAR_MASK (0x02000000)
    #define SMMU_BGR_REG_SMMU_PCIE1_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_PCIE1_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_PCIE0_RST_OFFSET 24
  #define SMMU_BGR_REG_SMMU_PCIE0_RST_CLEAR_MASK (0x01000000)
    #define SMMU_BGR_REG_SMMU_PCIE0_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_PCIE0_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_MSI_LITE1_RST_OFFSET 23
  #define SMMU_BGR_REG_SMMU_MSI_LITE1_RST_CLEAR_MASK (0x00800000)
    #define SMMU_BGR_REG_SMMU_MSI_LITE1_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_MSI_LITE1_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_MSI_LITE0_RST_OFFSET 22
  #define SMMU_BGR_REG_SMMU_MSI_LITE0_RST_CLEAR_MASK (0x00400000)
    #define SMMU_BGR_REG_SMMU_MSI_LITE0_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_MSI_LITE0_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_USB3_RST_OFFSET 21
  #define SMMU_BGR_REG_SMMU_USB3_RST_CLEAR_MASK (0x00200000)
    #define SMMU_BGR_REG_SMMU_USB3_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_USB3_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_GMAC1_RST_OFFSET 20
  #define SMMU_BGR_REG_SMMU_GMAC1_RST_CLEAR_MASK (0x00100000)
    #define SMMU_BGR_REG_SMMU_GMAC1_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_GMAC1_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_GMAC0_RST_OFFSET 19
  #define SMMU_BGR_REG_SMMU_GMAC0_RST_CLEAR_MASK (0x00080000)
    #define SMMU_BGR_REG_SMMU_GMAC0_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_GMAC0_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_DE1_RST_OFFSET 18
  #define SMMU_BGR_REG_SMMU_DE1_RST_CLEAR_MASK (0x00040000)
    #define SMMU_BGR_REG_SMMU_DE1_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_DE1_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_DE0_RST_OFFSET 17
  #define SMMU_BGR_REG_SMMU_DE0_RST_CLEAR_MASK (0x00020000)
    #define SMMU_BGR_REG_SMMU_DE0_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_DE0_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_VE_DEC1_RST_OFFSET 16
  #define SMMU_BGR_REG_SMMU_VE_DEC1_RST_CLEAR_MASK (0x00010000)
    #define SMMU_BGR_REG_SMMU_VE_DEC1_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_VE_DEC1_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_VE_DEC0_RST_OFFSET 15
  #define SMMU_BGR_REG_SMMU_VE_DEC0_RST_CLEAR_MASK (0x00008000)
    #define SMMU_BGR_REG_SMMU_VE_DEC0_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_VE_DEC0_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_VE_ENC1_RST_OFFSET 14
  #define SMMU_BGR_REG_SMMU_VE_ENC1_RST_CLEAR_MASK (0x00004000)
    #define SMMU_BGR_REG_SMMU_VE_ENC1_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_VE_ENC1_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_VE_ENC0_RST_OFFSET 13
  #define SMMU_BGR_REG_SMMU_VE_ENC0_RST_CLEAR_MASK (0x00002000)
    #define SMMU_BGR_REG_SMMU_VE_ENC0_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_VE_ENC0_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_G2D_RST_OFFSET 12
  #define SMMU_BGR_REG_SMMU_G2D_RST_CLEAR_MASK (0x00001000)
    #define SMMU_BGR_REG_SMMU_G2D_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_G2D_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_DI_RST_OFFSET 11
  #define SMMU_BGR_REG_SMMU_DI_RST_CLEAR_MASK (0x00000800)
    #define SMMU_BGR_REG_SMMU_DI_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_DI_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_CSI_DMA1_RST_OFFSET 10
  #define SMMU_BGR_REG_SMMU_CSI_DMA1_RST_CLEAR_MASK (0x00000400)
    #define SMMU_BGR_REG_SMMU_CSI_DMA1_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_CSI_DMA1_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_CSI_DMA0_RST_OFFSET 9
  #define SMMU_BGR_REG_SMMU_CSI_DMA0_RST_CLEAR_MASK (0x00000200)
    #define SMMU_BGR_REG_SMMU_CSI_DMA0_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_CSI_DMA0_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_ISP_RST_OFFSET 8
  #define SMMU_BGR_REG_SMMU_ISP_RST_CLEAR_MASK (0x00000100)
    #define SMMU_BGR_REG_SMMU_ISP_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_ISP_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_SYS_RST_OFFSET 4
  #define SMMU_BGR_REG_SMMU_SYS_RST_CLEAR_MASK (0x00000010)
    #define SMMU_BGR_REG_SMMU_SYS_RST_ASSERT (0b0)
    #define SMMU_BGR_REG_SMMU_SYS_RST_DE_ASSERT (0b1)
  #define SMMU_BGR_REG_SMMU_GATING_OFFSET 0
  #define SMMU_BGR_REG_SMMU_GATING_CLEAR_MASK (0x00000001)
    #define SMMU_BGR_REG_SMMU_GATING_MASK (0x0)
    #define SMMU_BGR_REG_SMMU_GATING_PASS (0b1)

#define MSI_LITE0_BGR_REG 0x00000594 //MSI_LITE0 Bus Gating Reset Register
  #define MSI_LITE0_BGR_REG_MSI_LITE0_RST_OFFSET 16
  #define MSI_LITE0_BGR_REG_MSI_LITE0_RST_CLEAR_MASK (0x00010000)
    #define MSI_LITE0_BGR_REG_MSI_LITE0_RST_ASSERT (0b0)
    #define MSI_LITE0_BGR_REG_MSI_LITE0_RST_DE_ASSERT (0b1)
  #define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_OFFSET 0
  #define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_CLEAR_MASK (0x00000001)
    #define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_MASK (0x0)
    #define MSI_LITE0_BGR_REG_MSI_LITE0_GATING_PASS (0b1)

#define MSI_LITE1_BGR_REG 0x0000059c //MSI_LITE1 Bus Gating Reset Register
  #define MSI_LITE1_BGR_REG_MSI_LITE1_RST_OFFSET 16
  #define MSI_LITE1_BGR_REG_MSI_LITE1_RST_CLEAR_MASK (0x00010000)
    #define MSI_LITE1_BGR_REG_MSI_LITE1_RST_ASSERT (0b0)
    #define MSI_LITE1_BGR_REG_MSI_LITE1_RST_DE_ASSERT (0b1)
  #define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_OFFSET 0
  #define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_CLEAR_MASK (0x00000001)
    #define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_MASK (0x0)
    #define MSI_LITE1_BGR_REG_MSI_LITE1_GATING_PASS (0b1)

#define AHB_GATE_EN_REG 0x000005c0 //AHB Gate Enable Register
  #define AHB_GATE_EN_REG_AHB_MONITOR_EN_OFFSET 31
  #define AHB_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK (0x80000000)
    #define AHB_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE (0b0)
    #define AHB_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE (0b1)
  #define AHB_GATE_EN_REG_SD_MONITOR_EN_OFFSET 29
  #define AHB_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK (0x20000000)
    #define AHB_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE (0b0)
    #define AHB_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE (0b1)
  #define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET 28
  #define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK (0x10000000)
    #define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE (0b0)
    #define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE (0b1)
  #define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_OFFSET 14
  #define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK (0x00004000)
    #define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_DISABLE (0b0)
    #define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_ENABLE (0b1)
  #define AHB_GATE_EN_REG_SERDES_AHB_GATE_SW_CFG_OFFSET 13
  #define AHB_GATE_EN_REG_SERDES_AHB_GATE_SW_CFG_CLEAR_MASK (0x00002000)
    #define AHB_GATE_EN_REG_SERDES_AHB_GATE_SW_CFG_DISABLE (0b0)
    #define AHB_GATE_EN_REG_SERDES_AHB_GATE_SW_CFG_ENABLE (0b1)
  #define AHB_GATE_EN_REG_GPU0_AHB_GATE_SW_CFG_OFFSET 10
  #define AHB_GATE_EN_REG_GPU0_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000400)
    #define AHB_GATE_EN_REG_GPU0_AHB_GATE_SW_CFG_DISABLE (0b0)
    #define AHB_GATE_EN_REG_GPU0_AHB_GATE_SW_CFG_ENABLE (0b1)
  #define AHB_GATE_EN_REG_SMHC3_AHB_GATE_SW_CFG_OFFSET 8
  #define AHB_GATE_EN_REG_SMHC3_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000100)
    #define AHB_GATE_EN_REG_SMHC3_AHB_GATE_SW_CFG_DISABLE (0b0)
    #define AHB_GATE_EN_REG_SMHC3_AHB_GATE_SW_CFG_ENABLE (0b1)
  #define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET 7
  #define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000080)
    #define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE (0b0)
    #define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE (0b1)
  #define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET 6
  #define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000040)
    #define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE (0b0)
    #define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE (0b1)
  #define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET 5
  #define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000020)
    #define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE (0b0)
    #define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE (0b1)
  #define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_OFFSET 3
  #define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000008)
    #define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_DISABLE (0b0)
    #define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_ENABLE (0b1)
  #define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET 2
  #define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000004)
    #define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE (0b0)
    #define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE (0b1)
  #define AHB_GATE_EN_REG_VE_ENC_AHB_GATE_SW_CFG_OFFSET 1
  #define AHB_GATE_EN_REG_VE_ENC_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000002)
    #define AHB_GATE_EN_REG_VE_ENC_AHB_GATE_SW_CFG_DISABLE (0b0)
    #define AHB_GATE_EN_REG_VE_ENC_AHB_GATE_SW_CFG_ENABLE (0b1)
  #define AHB_GATE_EN_REG_VE_DEC_AHB_GATE_SW_CFG_OFFSET 0
  #define AHB_GATE_EN_REG_VE_DEC_AHB_GATE_SW_CFG_CLEAR_MASK (0x00000001)
    #define AHB_GATE_EN_REG_VE_DEC_AHB_GATE_SW_CFG_DISABLE (0b0)
    #define AHB_GATE_EN_REG_VE_DEC_AHB_GATE_SW_CFG_ENABLE (0b1)

#define MBUS_GATE_EN_REG 0x000005e0 //MBUS Gate Enable Register
  #define MBUS_GATE_EN_REG_MSILITE2_MBUS_GATE_SW_CFG_OFFSET 31
  #define MBUS_GATE_EN_REG_MSILITE2_MBUS_GATE_SW_CFG_CLEAR_MASK (0x80000000)
    #define MBUS_GATE_EN_REG_MSILITE2_MBUS_GATE_SW_CFG_DISABLE (0b0)
    #define MBUS_GATE_EN_REG_MSILITE2_MBUS_GATE_SW_CFG_ENABLE (0b1)
  #define MBUS_GATE_EN_REG_MSILITE0_MBUS_GATE_SW_CFG_OFFSET 29
  #define MBUS_GATE_EN_REG_MSILITE0_MBUS_GATE_SW_CFG_CLEAR_MASK (0x20000000)
    #define MBUS_GATE_EN_REG_MSILITE0_MBUS_GATE_SW_CFG_DISABLE (0b0)
    #define MBUS_GATE_EN_REG_MSILITE0_MBUS_GATE_SW_CFG_ENABLE (0b1)
  #define MBUS_GATE_EN_REG_SERDES_MBUS_GATE_SW_CFG_OFFSET 28
  #define MBUS_GATE_EN_REG_SERDES_MBUS_GATE_SW_CFG_CLEAR_MASK (0x10000000)
    #define MBUS_GATE_EN_REG_SERDES_MBUS_GATE_SW_CFG_DISABLE (0b0)
    #define MBUS_GATE_EN_REG_SERDES_MBUS_GATE_SW_CFG_ENABLE (0b1)
  #define MBUS_GATE_EN_REG_TCU_MBUS_GATE_SW_CFG_OFFSET 27
  #define MBUS_GATE_EN_REG_TCU_MBUS_GATE_SW_CFG_CLEAR_MASK (0x08000000)
    #define MBUS_GATE_EN_REG_TCU_MBUS_GATE_SW_CFG_DISABLE (0b0)
    #define MBUS_GATE_EN_REG_TCU_MBUS_GATE_SW_CFG_ENABLE (0b1)
  #define MBUS_GATE_EN_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET 24
  #define MBUS_GATE_EN_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK (0x01000000)
    #define MBUS_GATE_EN_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE (0b0)
    #define MBUS_GATE_EN_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE (0b1)
  #define MBUS_GATE_EN_REG_AIPU_MBUS_GATE_SW_CFG_OFFSET 19
  #define MBUS_GATE_EN_REG_AIPU_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00080000)
    #define MBUS_GATE_EN_REG_AIPU_MBUS_GATE_SW_CFG_DISABLE (0b0)
    #define MBUS_GATE_EN_REG_AIPU_MBUS_GATE_SW_CFG_ENABLE (0b1)
  #define MBUS_GATE_EN_REG_NPU_MBUS_GATE_SW_CFG_OFFSET 18
  #define MBUS_GATE_EN_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00040000)
    #define MBUS_GATE_EN_REG_NPU_MBUS_GATE_SW_CFG_DISABLE (0b0)
    #define MBUS_GATE_EN_REG_NPU_MBUS_GATE_SW_CFG_ENABLE (0b1)
  #define MBUS_GATE_EN_REG_GPU0_MBUS_GATE_SW_CFG_OFFSET 16
  #define MBUS_GATE_EN_REG_GPU0_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00010000)
    #define MBUS_GATE_EN_REG_GPU0_MBUS_GATE_SW_CFG_DISABLE (0b0)
    #define MBUS_GATE_EN_REG_GPU0_MBUS_GATE_SW_CFG_ENABLE (0b1)
  #define MBUS_GATE_EN_REG_VE_DEC_MBUS_GATE_SW_CFG_OFFSET 14
  #define MBUS_GATE_EN_REG_VE_DEC_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00004000)
    #define MBUS_GATE_EN_REG_VE_DEC_MBUS_GATE_SW_CFG_DISABLE (0b0)
    #define MBUS_GATE_EN_REG_VE_DEC_MBUS_GATE_SW_CFG_ENABLE (0b1)
  #define MBUS_GATE_EN_REG_VE_ENC1_MBUS_GATE_SW_CFG_OFFSET 13
  #define MBUS_GATE_EN_REG_VE_ENC1_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00002000)
    #define MBUS_GATE_EN_REG_VE_ENC1_MBUS_GATE_SW_CFG_DISABLE (0b0)
    #define MBUS_GATE_EN_REG_VE_ENC1_MBUS_GATE_SW_CFG_ENABLE (0b1)
  #define MBUS_GATE_EN_REG_VE_ENC0_MBUS_GATE_SW_CFG_OFFSET 12
  #define MBUS_GATE_EN_REG_VE_ENC0_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00001000)
    #define MBUS_GATE_EN_REG_VE_ENC0_MBUS_GATE_SW_CFG_DISABLE (0b0)
    #define MBUS_GATE_EN_REG_VE_ENC0_MBUS_GATE_SW_CFG_ENABLE (0b1)
  #define MBUS_GATE_EN_REG_DESYS_MBUS_GATE_SW_CFG_OFFSET 11
  #define MBUS_GATE_EN_REG_DESYS_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00000800)
    #define MBUS_GATE_EN_REG_DESYS_MBUS_GATE_SW_CFG_DISABLE (0b0)
    #define MBUS_GATE_EN_REG_DESYS_MBUS_GATE_SW_CFG_ENABLE (0b1)
  #define MBUS_GATE_EN_REG_NAND_MBUS_GATE_SW_CFG_OFFSET 2
  #define MBUS_GATE_EN_REG_NAND_MBUS_GATE_SW_CFG_CLEAR_MASK (0x00000004)
    #define MBUS_GATE_EN_REG_NAND_MBUS_GATE_SW_CFG_DISABLE (0b0)
    #define MBUS_GATE_EN_REG_NAND_MBUS_GATE_SW_CFG_ENABLE (0b1)

#define MBUS_MAT_CLK_GATING_REG 0x000005e4 //MBUS Master Clock Gating Register
  #define MBUS_MAT_CLK_GATING_REG_VE_ENC1_MCLK_EN_OFFSET 19
  #define MBUS_MAT_CLK_GATING_REG_VE_ENC1_MCLK_EN_CLEAR_MASK (0x00080000)
    #define MBUS_MAT_CLK_GATING_REG_VE_ENC1_MCLK_EN_MASK (0x0)
    #define MBUS_MAT_CLK_GATING_REG_VE_ENC1_MCLK_EN_PASS (0b1)
  #define MBUS_MAT_CLK_GATING_REG_VE_DEC_MCLK_EN_OFFSET 18
  #define MBUS_MAT_CLK_GATING_REG_VE_DEC_MCLK_EN_CLEAR_MASK (0x00040000)
    #define MBUS_MAT_CLK_GATING_REG_VE_DEC_MCLK_EN_MASK (0x0)
    #define MBUS_MAT_CLK_GATING_REG_VE_DEC_MCLK_EN_PASS (0b1)
  #define MBUS_MAT_CLK_GATING_REG_CAN_MCLK_EN_OFFSET 17
  #define MBUS_MAT_CLK_GATING_REG_CAN_MCLK_EN_CLEAR_MASK (0x00020000)
    #define MBUS_MAT_CLK_GATING_REG_CAN_MCLK_EN_MASK (0x0)
    #define MBUS_MAT_CLK_GATING_REG_CAN_MCLK_EN_PASS (0b1)
  #define MBUS_MAT_CLK_GATING_REG_GMAC1_MCLK_EN_OFFSET 12
  #define MBUS_MAT_CLK_GATING_REG_GMAC1_MCLK_EN_CLEAR_MASK (0x00001000)
    #define MBUS_MAT_CLK_GATING_REG_GMAC1_MCLK_EN_MASK (0x0)
    #define MBUS_MAT_CLK_GATING_REG_GMAC1_MCLK_EN_PASS (0b1)
  #define MBUS_MAT_CLK_GATING_REG_GMAC0_MCLK_EN_OFFSET 11
  #define MBUS_MAT_CLK_GATING_REG_GMAC0_MCLK_EN_CLEAR_MASK (0x00000800)
    #define MBUS_MAT_CLK_GATING_REG_GMAC0_MCLK_EN_MASK (0x0)
    #define MBUS_MAT_CLK_GATING_REG_GMAC0_MCLK_EN_PASS (0b1)
  #define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_OFFSET 9
  #define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_CLEAR_MASK (0x00000200)
    #define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_MASK (0x0)
    #define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_PASS (0b1)
  #define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_OFFSET 8
  #define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_CLEAR_MASK (0x00000100)
    #define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_MASK (0x0)
    #define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_PASS (0b1)
  #define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_OFFSET 5
  #define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_CLEAR_MASK (0x00000020)
    #define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_MASK (0x0)
    #define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_PASS (0b1)
  #define MBUS_MAT_CLK_GATING_REG_DMA1_MCLK_EN_OFFSET 3
  #define MBUS_MAT_CLK_GATING_REG_DMA1_MCLK_EN_CLEAR_MASK (0x00000008)
    #define MBUS_MAT_CLK_GATING_REG_DMA1_MCLK_EN_MASK (0x0)
    #define MBUS_MAT_CLK_GATING_REG_DMA1_MCLK_EN_PASS (0b1)
  #define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_OFFSET 2
  #define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_CLEAR_MASK (0x00000004)
    #define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_MASK (0x0)
    #define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_SECURE_DEBUG (0b1)
  #define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MCLK_EN_OFFSET 1
  #define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MCLK_EN_CLEAR_MASK (0x00000002)
    #define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MCLK_EN_MASK (0x0)
    #define MBUS_MAT_CLK_GATING_REG_VE_ENC0_MCLK_EN_PASS (0b1)
  #define MBUS_MAT_CLK_GATING_REG_DMA0_MCLK_EN_OFFSET 0
  #define MBUS_MAT_CLK_GATING_REG_DMA0_MCLK_EN_CLEAR_MASK (0x00000001)
    #define MBUS_MAT_CLK_GATING_REG_DMA0_MCLK_EN_MASK (0x0)
    #define MBUS_MAT_CLK_GATING_REG_DMA0_MCLK_EN_PASS (0b1)

#define DMA0_BGR_REG 0x00000704 //DMA0 Bus Gating Reset Register
  #define DMA0_BGR_REG_DMA0_RST_OFFSET 16
  #define DMA0_BGR_REG_DMA0_RST_CLEAR_MASK (0x00010000)
    #define DMA0_BGR_REG_DMA0_RST_ASSERT (0b0)
    #define DMA0_BGR_REG_DMA0_RST_DE_ASSERT (0b1)
  #define DMA0_BGR_REG_DMA0_GATING_OFFSET 0
  #define DMA0_BGR_REG_DMA0_GATING_CLEAR_MASK (0x00000001)
    #define DMA0_BGR_REG_DMA0_GATING_MASK (0x0)
    #define DMA0_BGR_REG_DMA0_GATING_PASS (0b1)

#define DMA1_BGR_REG 0x0000070c //DMA1 Bus Gating Reset Register
  #define DMA1_BGR_REG_DMA1_RST_OFFSET 16
  #define DMA1_BGR_REG_DMA1_RST_CLEAR_MASK (0x00010000)
    #define DMA1_BGR_REG_DMA1_RST_ASSERT (0b0)
    #define DMA1_BGR_REG_DMA1_RST_DE_ASSERT (0b1)
  #define DMA1_BGR_REG_DMA1_GATING_OFFSET 0
  #define DMA1_BGR_REG_DMA1_GATING_CLEAR_MASK (0x00000001)
    #define DMA1_BGR_REG_DMA1_GATING_MASK (0x0)
    #define DMA1_BGR_REG_DMA1_GATING_PASS (0b1)

#define SPINLOCK_BGR_REG 0x00000724 //SPINLOCK Bus Gating Reset Register
  #define SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET 16
  #define SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK (0x00010000)
    #define SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT (0b0)
    #define SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT (0b1)
  #define SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET 0
  #define SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK (0x00000001)
    #define SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK (0x0)
    #define SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS (0b1)

#define MSGBOX0_BGR_REG 0x00000744 //MSGBOX0 Bus Gating Reset Register
  #define MSGBOX0_BGR_REG_MSGBOX0_RST_OFFSET 16
  #define MSGBOX0_BGR_REG_MSGBOX0_RST_CLEAR_MASK (0x00010000)
    #define MSGBOX0_BGR_REG_MSGBOX0_RST_ASSERT (0b0)
    #define MSGBOX0_BGR_REG_MSGBOX0_RST_DE_ASSERT (0b1)
  #define MSGBOX0_BGR_REG_MSGBOX0_GATING_OFFSET 0
  #define MSGBOX0_BGR_REG_MSGBOX0_GATING_CLEAR_MASK (0x00000001)
    #define MSGBOX0_BGR_REG_MSGBOX0_GATING_MASK (0x0)
    #define MSGBOX0_BGR_REG_MSGBOX0_GATING_PASS (0b1)

#define MSGBOX1_BGR_REG 0x0000074c //MSGBOX1 Bus Gating Reset register
  #define MSGBOX1_BGR_REG_MSGBOX1_RST_OFFSET 16
  #define MSGBOX1_BGR_REG_MSGBOX1_RST_CLEAR_MASK (0x00010000)
    #define MSGBOX1_BGR_REG_MSGBOX1_RST_ASSERT (0b0)
    #define MSGBOX1_BGR_REG_MSGBOX1_RST_DE_ASSERT (0b1)
  #define MSGBOX1_BGR_REG_MSGBOX1_GATING_OFFSET 0
  #define MSGBOX1_BGR_REG_MSGBOX1_GATING_CLEAR_MASK (0x00000001)
    #define MSGBOX1_BGR_REG_MSGBOX1_GATING_MASK (0x0)
    #define MSGBOX1_BGR_REG_MSGBOX1_GATING_PASS (0b1)

#define MSGBOX2_BGR_REG 0x00000754 //MSGBOX2 Bus Gating Reset Register
  #define MSGBOX2_BGR_REG_MSGBOX2_RST_OFFSET 16
  #define MSGBOX2_BGR_REG_MSGBOX2_RST_CLEAR_MASK (0x00010000)
    #define MSGBOX2_BGR_REG_MSGBOX2_RST_ASSERT (0b0)
    #define MSGBOX2_BGR_REG_MSGBOX2_RST_DE_ASSERT (0b1)
  #define MSGBOX2_BGR_REG_MSGBOX2_GATING_OFFSET 0
  #define MSGBOX2_BGR_REG_MSGBOX2_GATING_CLEAR_MASK (0x00000001)
    #define MSGBOX2_BGR_REG_MSGBOX2_GATING_MASK (0x0)
    #define MSGBOX2_BGR_REG_MSGBOX2_GATING_PASS (0b1)

#define PWM0_BGR_REG 0x00000784 //PWM0 Bus Gating Reset Register
  #define PWM0_BGR_REG_PWM0_RST_OFFSET 16
  #define PWM0_BGR_REG_PWM0_RST_CLEAR_MASK (0x00010000)
    #define PWM0_BGR_REG_PWM0_RST_ASSERT (0b0)
    #define PWM0_BGR_REG_PWM0_RST_DE_ASSERT (0b1)
  #define PWM0_BGR_REG_PWM0_GATING_OFFSET 0
  #define PWM0_BGR_REG_PWM0_GATING_CLEAR_MASK (0x00000001)
    #define PWM0_BGR_REG_PWM0_GATING_MASK (0x0)
    #define PWM0_BGR_REG_PWM0_GATING_PASS (0b1)

#define PWM1_BGR_REG 0x0000078c //PWM1 Bus Gating Reset Register
  #define PWM1_BGR_REG_PWM1_RST_OFFSET 16
  #define PWM1_BGR_REG_PWM1_RST_CLEAR_MASK (0x00010000)
    #define PWM1_BGR_REG_PWM1_RST_ASSERT (0b0)
    #define PWM1_BGR_REG_PWM1_RST_DE_ASSERT (0b1)
  #define PWM1_BGR_REG_PWM1_GATING_OFFSET 0
  #define PWM1_BGR_REG_PWM1_GATING_CLEAR_MASK (0x00000001)
    #define PWM1_BGR_REG_PWM1_GATING_MASK (0x0)
    #define PWM1_BGR_REG_PWM1_GATING_PASS (0b1)

#define DBGSYS_BGR_REG 0x000007a4 //DBGSYS Bus Gating Reset Register
  #define DBGSYS_BGR_REG_DBGSYS_RST_OFFSET 16
  #define DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK (0x00010000)
    #define DBGSYS_BGR_REG_DBGSYS_RST_ASSERT (0b0)
    #define DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT (0b1)
  #define DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET 0
  #define DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK (0x00000001)
    #define DBGSYS_BGR_REG_DBGSYS_GATING_MASK (0x0)
    #define DBGSYS_BGR_REG_DBGSYS_GATING_PASS (0b1)

#define SYSDAP_BGR_REG 0x000007ac //SYSDAP Bus Gating Reset Register
  #define SYSDAP_BGR_REG_SYSDAP_RST_OFFSET 16
  #define SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK (0x00010000)
    #define SYSDAP_BGR_REG_SYSDAP_RST_ASSERT (0b0)
    #define SYSDAP_BGR_REG_SYSDAP_RST_SECURE_DEBUG (0b1)
  #define SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET 0
  #define SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK (0x00000001)
    #define SYSDAP_BGR_REG_SYSDAP_GATING_MASK (0x0)
    #define SYSDAP_BGR_REG_SYSDAP_GATING_SECURE_DEBUG (0b1)

#define TIMER0_CLK0_CLK_REG 0x00000800 //TIMER0_CLK0 Clock Register
  #define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_OFFSET 31
  #define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_DISABLE (0b0)
    #define TIMER0_CLK0_CLK_REG_TIMER0_CLK0_CLK_GATING_ENABLE (0b1)
  #define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER0_CLK0_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER0_CLK0_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER0_CLK0_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER0_CLK0_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER0_CLK0_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER0_CLK0_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER0_CLK0_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER0_CLK0_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER0_CLK0_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER0_CLK0_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER0_CLK0_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER0_CLK1_CLK_REG 0x00000804 //TIMER0_CLK1 Clock Register
  #define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_OFFSET 31
  #define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_DISABLE (0b0)
    #define TIMER0_CLK1_CLK_REG_TIMER0_CLK1_CLK_GATING_ENABLE (0b1)
  #define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER0_CLK1_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER0_CLK1_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER0_CLK1_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER0_CLK1_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER0_CLK1_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER0_CLK1_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER0_CLK1_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER0_CLK1_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER0_CLK1_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER0_CLK1_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER0_CLK2_CLK_REG 0x00000808 //TIMER0_CLK2 Clock Register
  #define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_OFFSET 31
  #define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_DISABLE (0b0)
    #define TIMER0_CLK2_CLK_REG_TIMER0_CLK2_CLK_GATING_ENABLE (0b1)
  #define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER0_CLK2_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER0_CLK2_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER0_CLK2_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER0_CLK2_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER0_CLK2_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER0_CLK2_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER0_CLK2_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER0_CLK2_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER0_CLK2_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER0_CLK2_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER0_CLK2_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER0_CLK3_CLK_REG 0x0000080c //TIMER0_CLK3 Clock Register
  #define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_OFFSET 31
  #define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_DISABLE (0b0)
    #define TIMER0_CLK3_CLK_REG_TIMER0_CLK3_CLK_GATING_ENABLE (0b1)
  #define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER0_CLK3_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER0_CLK3_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER0_CLK3_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER0_CLK3_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER0_CLK3_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER0_CLK3_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER0_CLK3_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER0_CLK3_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER0_CLK3_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER0_CLK3_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER0_CLK3_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER0_CLK4_CLK_REG 0x00000810 //TIMER0_CLK4 Clock Register
  #define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_OFFSET 31
  #define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_DISABLE (0b0)
    #define TIMER0_CLK4_CLK_REG_TIMER0_CLK4_CLK_GATING_ENABLE (0b1)
  #define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER0_CLK4_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER0_CLK4_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER0_CLK4_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER0_CLK4_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER0_CLK4_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER0_CLK4_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER0_CLK4_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER0_CLK4_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER0_CLK4_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER0_CLK4_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER0_CLK4_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER0_CLK5_CLK_REG 0x00000814 //TIMER0_CLK5 Clock Register
  #define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_OFFSET 31
  #define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_DISABLE (0b0)
    #define TIMER0_CLK5_CLK_REG_TIMER0_CLK5_CLK_GATING_ENABLE (0b1)
  #define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER0_CLK5_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER0_CLK5_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER0_CLK5_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER0_CLK5_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER0_CLK5_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER0_CLK5_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER0_CLK5_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER0_CLK5_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER0_CLK5_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER0_CLK5_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER0_CLK5_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER0_CLK6_CLK_REG 0x00000818 //TIMER0_CLK6 Clock Register
  #define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_OFFSET 31
  #define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_DISABLE (0b0)
    #define TIMER0_CLK6_CLK_REG_TIMER0_CLK6_CLK_GATING_ENABLE (0b1)
  #define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER0_CLK6_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER0_CLK6_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER0_CLK6_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER0_CLK6_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER0_CLK6_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER0_CLK6_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER0_CLK6_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER0_CLK6_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER0_CLK6_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER0_CLK6_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER0_CLK6_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER0_CLK7_CLK_REG 0x0000081c //TIMER0_CLK7 Clock Register
  #define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_OFFSET 31
  #define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_DISABLE (0b0)
    #define TIMER0_CLK7_CLK_REG_TIMER0_CLK7_CLK_GATING_ENABLE (0b1)
  #define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER0_CLK7_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER0_CLK7_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER0_CLK7_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER0_CLK7_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER0_CLK7_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER0_CLK7_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER0_CLK7_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER0_CLK7_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER0_CLK7_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER0_CLK7_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER0_CLK7_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER0_CLK8_CLK_REG 0x00000820 //TIMER0_CLK8 Clock Register
  #define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_OFFSET 31
  #define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_DISABLE (0b0)
    #define TIMER0_CLK8_CLK_REG_TIMER0_CLK8_CLK_GATING_ENABLE (0b1)
  #define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER0_CLK8_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER0_CLK8_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER0_CLK8_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER0_CLK8_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER0_CLK8_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER0_CLK8_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER0_CLK8_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER0_CLK8_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER0_CLK8_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER0_CLK8_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER0_CLK8_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER0_CLK9_CLK_REG 0x00000824 //TIMER0_CLK9 Clock Register
  #define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_OFFSET 31
  #define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_DISABLE (0b0)
    #define TIMER0_CLK9_CLK_REG_TIMER0_CLK9_CLK_GATING_ENABLE (0b1)
  #define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER0_CLK9_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER0_CLK9_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER0_CLK9_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER0_CLK9_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER0_CLK9_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER0_CLK9_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER0_CLK9_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER0_CLK9_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER0_CLK9_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER0_CLK9_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER0_CLK9_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER0_BGR_REG 0x00000850 //TIMER0 Bus Gating Reset Register
  #define TIMER0_BGR_REG_TIMER0_RST_OFFSET 16
  #define TIMER0_BGR_REG_TIMER0_RST_CLEAR_MASK (0x00010000)
    #define TIMER0_BGR_REG_TIMER0_RST_ASSERT (0b0)
    #define TIMER0_BGR_REG_TIMER0_RST_DE_ASSERT (0b1)
  #define TIMER0_BGR_REG_TIMER0_GATING_OFFSET 0
  #define TIMER0_BGR_REG_TIMER0_GATING_CLEAR_MASK (0x00000001)
    #define TIMER0_BGR_REG_TIMER0_GATING_MASK (0x0)
    #define TIMER0_BGR_REG_TIMER0_GATING_PASS (0b1)

#define TIMER1_CLK0_CLK_REG 0x00000880 //TIMER1_CLK0 Clock Register
  #define TIMER1_CLK0_CLK_REG_TIMER1_CLK0_CLK_GATING_OFFSET 31
  #define TIMER1_CLK0_CLK_REG_TIMER1_CLK0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER1_CLK0_CLK_REG_TIMER1_CLK0_CLK_GATING_DISABLE (0b0)
    #define TIMER1_CLK0_CLK_REG_TIMER1_CLK0_CLK_GATING_ENABLE (0b1)
  #define TIMER1_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER1_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER1_CLK0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER1_CLK0_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER1_CLK0_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER1_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER1_CLK0_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER1_CLK0_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER1_CLK0_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER1_CLK0_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER1_CLK0_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER1_CLK0_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER1_CLK0_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER1_CLK0_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER1_CLK0_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER1_CLK0_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER1_CLK0_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER1_CLK1_CLK_REG 0x00000884 //TIMER1_CLK1 Clock Register
  #define TIMER1_CLK1_CLK_REG_TIMER1_CLK1_CLK_GATING_OFFSET 31
  #define TIMER1_CLK1_CLK_REG_TIMER1_CLK1_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER1_CLK1_CLK_REG_TIMER1_CLK1_CLK_GATING_DISABLE (0b0)
    #define TIMER1_CLK1_CLK_REG_TIMER1_CLK1_CLK_GATING_ENABLE (0b1)
  #define TIMER1_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER1_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER1_CLK1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER1_CLK1_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER1_CLK1_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER1_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER1_CLK1_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER1_CLK1_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER1_CLK1_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER1_CLK1_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER1_CLK1_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER1_CLK1_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER1_CLK1_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER1_CLK1_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER1_CLK1_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER1_CLK1_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER1_CLK1_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER1_CLK2_CLK_REG 0x00000888 //TIMER1_CLK2 Clock Register
  #define TIMER1_CLK2_CLK_REG_TIMER1_CLK2_CLK_GATING_OFFSET 31
  #define TIMER1_CLK2_CLK_REG_TIMER1_CLK2_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER1_CLK2_CLK_REG_TIMER1_CLK2_CLK_GATING_DISABLE (0b0)
    #define TIMER1_CLK2_CLK_REG_TIMER1_CLK2_CLK_GATING_ENABLE (0b1)
  #define TIMER1_CLK2_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER1_CLK2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER1_CLK2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER1_CLK2_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER1_CLK2_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER1_CLK2_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER1_CLK2_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER1_CLK2_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER1_CLK2_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER1_CLK2_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER1_CLK2_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER1_CLK2_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER1_CLK2_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER1_CLK2_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER1_CLK2_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER1_CLK2_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER1_CLK2_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER1_CLK3_CLK_REG 0x0000088c //TIMER1_CLK3 Clock Register
  #define TIMER1_CLK3_CLK_REG_TIMER1_CLK3_CLK_GATING_OFFSET 31
  #define TIMER1_CLK3_CLK_REG_TIMER1_CLK3_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER1_CLK3_CLK_REG_TIMER1_CLK3_CLK_GATING_DISABLE (0b0)
    #define TIMER1_CLK3_CLK_REG_TIMER1_CLK3_CLK_GATING_ENABLE (0b1)
  #define TIMER1_CLK3_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER1_CLK3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER1_CLK3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER1_CLK3_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER1_CLK3_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER1_CLK3_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER1_CLK3_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER1_CLK3_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER1_CLK3_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER1_CLK3_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER1_CLK3_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER1_CLK3_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER1_CLK3_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER1_CLK3_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER1_CLK3_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER1_CLK3_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER1_CLK3_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER1_CLK4_CLK_REG 0x00000890 //TIMER1_CLK4 Clock Register
  #define TIMER1_CLK4_CLK_REG_TIMER1_CLK4_CLK_GATING_OFFSET 31
  #define TIMER1_CLK4_CLK_REG_TIMER1_CLK4_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER1_CLK4_CLK_REG_TIMER1_CLK4_CLK_GATING_DISABLE (0b0)
    #define TIMER1_CLK4_CLK_REG_TIMER1_CLK4_CLK_GATING_ENABLE (0b1)
  #define TIMER1_CLK4_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER1_CLK4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER1_CLK4_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER1_CLK4_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER1_CLK4_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER1_CLK4_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER1_CLK4_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER1_CLK4_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER1_CLK4_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER1_CLK4_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER1_CLK4_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER1_CLK4_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER1_CLK4_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER1_CLK4_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER1_CLK4_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER1_CLK4_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER1_CLK4_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER1_CLK5_CLK_REG 0x00000894 //TIMER1_CLK5 Clock Register
  #define TIMER1_CLK5_CLK_REG_TIMER1_CLK5_CLK_GATING_OFFSET 31
  #define TIMER1_CLK5_CLK_REG_TIMER1_CLK5_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TIMER1_CLK5_CLK_REG_TIMER1_CLK5_CLK_GATING_DISABLE (0b0)
    #define TIMER1_CLK5_CLK_REG_TIMER1_CLK5_CLK_GATING_ENABLE (0b1)
  #define TIMER1_CLK5_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER1_CLK5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TIMER1_CLK5_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define TIMER1_CLK5_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b001)
    #define TIMER1_CLK5_CLK_REG_CLK_SRC_SEL_CLK32K (0b010)
    #define TIMER1_CLK5_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b011)
    #define TIMER1_CLK5_CLK_REG_CLK_SRC_SEL_HOSC (0b100)
  #define TIMER1_CLK5_CLK_REG_FACTOR_P_OFFSET 0
  #define TIMER1_CLK5_CLK_REG_FACTOR_P_CLEAR_MASK (0x00000007)
    #define TIMER1_CLK5_CLK_REG_FACTOR_P__1 (0b000)
    #define TIMER1_CLK5_CLK_REG_FACTOR_P__2 (0b001)
    #define TIMER1_CLK5_CLK_REG_FACTOR_P__4 (0b010)
    #define TIMER1_CLK5_CLK_REG_FACTOR_P__8 (0b011)
    #define TIMER1_CLK5_CLK_REG_FACTOR_P__16 (0b100)
    #define TIMER1_CLK5_CLK_REG_FACTOR_P__32 (0b101)
    #define TIMER1_CLK5_CLK_REG_FACTOR_P__64 (0b110)
    #define TIMER1_CLK5_CLK_REG_FACTOR_P__128 (0b111)

#define TIMER1_BGR_REG 0x000008c0 //TIMER1 Bus Gating Reset Register
  #define TIMER1_BGR_REG_TIMER1_RST_OFFSET 16
  #define TIMER1_BGR_REG_TIMER1_RST_CLEAR_MASK (0x00010000)
    #define TIMER1_BGR_REG_TIMER1_RST_ASSERT (0b0)
    #define TIMER1_BGR_REG_TIMER1_RST_DE_ASSERT (0b1)
  #define TIMER1_BGR_REG_TIMER1_GATING_OFFSET 0
  #define TIMER1_BGR_REG_TIMER1_GATING_CLEAR_MASK (0x00000001)
    #define TIMER1_BGR_REG_TIMER1_GATING_MASK (0x0)
    #define TIMER1_BGR_REG_TIMER1_GATING_PASS (0b1)

#define DE0_CLK_REG 0x00000a00 //DE0 Clock Register
  #define DE0_CLK_REG_DE0_CLK_GATING_OFFSET 31
  #define DE0_CLK_REG_DE0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define DE0_CLK_REG_DE0_CLK_GATING_CLOCK_IS_ON (0b1)
  #define DE0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define DE0_CLK_REG_CLK_SRC_SEL_DEPLL3X (0b000)
    #define DE0_CLK_REG_CLK_SRC_SEL_DEPLL4X (0b001)
    #define DE0_CLK_REG_CLK_SRC_SEL_PERI0_480M (0b010)
    #define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M (0b011)
    #define DE0_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b100)
    #define DE0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b101)
    #define DE0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b110)
  #define DE0_CLK_REG_FACTOR_M_OFFSET 0
  #define DE0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define DE0_BGR_REG 0x00000a04 //DE0 Bus Gating Reset Register
  #define DE0_BGR_REG_DE0_RST_OFFSET 16
  #define DE0_BGR_REG_DE0_RST_CLEAR_MASK (0x00010000)
    #define DE0_BGR_REG_DE0_RST_ASSERT (0b0)
    #define DE0_BGR_REG_DE0_RST_DE_ASSERT (0b1)
  #define DE0_BGR_REG_DE0_GATING_OFFSET 0
  #define DE0_BGR_REG_DE0_GATING_CLEAR_MASK (0x00000001)
    #define DE0_BGR_REG_DE0_GATING_MASK (0x0)
    #define DE0_BGR_REG_DE0_GATING_PASS (0b1)

#define DE1_CLK_REG 0x00000a08 //DE1 Clock Register
  #define DE1_CLK_REG_DE1_CLK_GATING_OFFSET 31
  #define DE1_CLK_REG_DE1_CLK_GATING_CLEAR_MASK (0x80000000)
    #define DE1_CLK_REG_DE1_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define DE1_CLK_REG_DE1_CLK_GATING_CLOCK_IS_ON (0b1)
  #define DE1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define DE1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define DE1_CLK_REG_CLK_SRC_SEL_DEPLL3X (0b000)
    #define DE1_CLK_REG_CLK_SRC_SEL_DEPLL4X (0b001)
    #define DE1_CLK_REG_CLK_SRC_SEL_PERI0_480M (0b010)
    #define DE1_CLK_REG_CLK_SRC_SEL_PERI0_400M (0b011)
    #define DE1_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b100)
    #define DE1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b101)
    #define DE1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b110)
  #define DE1_CLK_REG_FACTOR_M_OFFSET 0
  #define DE1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define DE1_BGR_REG 0x00000a0c //DE1 Bus Gating Reset Register
  #define DE1_BGR_REG_DE1_RST_OFFSET 16
  #define DE1_BGR_REG_DE1_RST_CLEAR_MASK (0x00010000)
    #define DE1_BGR_REG_DE1_RST_ASSERT (0b0)
    #define DE1_BGR_REG_DE1_RST_DE_ASSERT (0b1)
  #define DE1_BGR_REG_DE1_GATING_OFFSET 0
  #define DE1_BGR_REG_DE1_GATING_CLEAR_MASK (0x00000001)
    #define DE1_BGR_REG_DE1_GATING_MASK (0x0)
    #define DE1_BGR_REG_DE1_GATING_PASS (0b1)

#define DI_CLK_REG 0x00000a20 //DI Clock Register
  #define DI_CLK_REG_DI_CLK_GATING_OFFSET 31
  #define DI_CLK_REG_DI_CLK_GATING_CLEAR_MASK (0x80000000)
    #define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_ON (0b1)
  #define DI_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define DI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define DI_CLK_REG_CLK_SRC_SEL_PERI0_480M (0b000)
    #define DI_CLK_REG_CLK_SRC_SEL_PERI0_600M (0b001)
    #define DI_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b010)
    #define DI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b011)
    #define DI_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b100)
  #define DI_CLK_REG_FACTOR_M_OFFSET 0
  #define DI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define DI_BGR_REG 0x00000a24 //DI Bus Gating Reset Register
  #define DI_BGR_REG_DI_RST_OFFSET 16
  #define DI_BGR_REG_DI_RST_CLEAR_MASK (0x00010000)
    #define DI_BGR_REG_DI_RST_ASSERT (0b0)
    #define DI_BGR_REG_DI_RST_DE_ASSERT (0b1)
  #define DI_BGR_REG_DI_GATING_OFFSET 0
  #define DI_BGR_REG_DI_GATING_CLEAR_MASK (0x00000001)
    #define DI_BGR_REG_DI_GATING_MASK (0x0)
    #define DI_BGR_REG_DI_GATING_PASS (0b1)

#define G2D_CLK_REG 0x00000a40 //G2D Clock Register
  #define G2D_CLK_REG_G2D_CLK_GATING_OFFSET 31
  #define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK (0x80000000)
    #define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON (0b1)
  #define G2D_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define G2D_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b000)
    #define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M (0b001)
    #define G2D_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b010)
    #define G2D_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b011)
  #define G2D_CLK_REG_FACTOR_M_OFFSET 0
  #define G2D_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define G2D_BGR_REG 0x00000a44 //G2D Bus Gating Reset Register
  #define G2D_BGR_REG_G2D_RST_OFFSET 16
  #define G2D_BGR_REG_G2D_RST_CLEAR_MASK (0x00010000)
    #define G2D_BGR_REG_G2D_RST_ASSERT (0b0)
    #define G2D_BGR_REG_G2D_RST_DE_ASSERT (0b1)
  #define G2D_BGR_REG_G2D_GATING_OFFSET 0
  #define G2D_BGR_REG_G2D_GATING_CLEAR_MASK (0x00000001)
    #define G2D_BGR_REG_G2D_GATING_MASK (0x0)
    #define G2D_BGR_REG_G2D_GATING_PASS (0b1)

#define DE_SYS_BGR_REG 0x00000a74 //DE_SYS Bus Gating Reset Register
  #define DE_SYS_BGR_REG_DE_SYS_RST_OFFSET 16
  #define DE_SYS_BGR_REG_DE_SYS_RST_CLEAR_MASK (0x00010000)
    #define DE_SYS_BGR_REG_DE_SYS_RST_ASSERT (0b0)
    #define DE_SYS_BGR_REG_DE_SYS_RST_DE_ASSERT (0b1)

#define VE_ENC0_CLK_REG 0x00000a80 //VE_ENC0 Clock Register
  #define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_OFFSET 31
  #define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define VE_ENC0_CLK_REG_VE_ENC0_CLK_GATING_CLOCK_IS_ON (0b1)
  #define VE_ENC0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define VE_ENC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define VE_ENC0_CLK_REG_CLK_SRC_SEL_VE0PLL (0b000)
    #define VE_ENC0_CLK_REG_CLK_SRC_SEL_VE1PLL (0b001)
    #define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_800M (0b010)
    #define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_600M (0b011)
    #define VE_ENC0_CLK_REG_CLK_SRC_SEL_PERI0_480M (0b100)
    #define VE_ENC0_CLK_REG_CLK_SRC_SEL_DEPLL3X (0b101)
    #define VE_ENC0_CLK_REG_CLK_SRC_SEL_NPUPLL (0b110)
  #define VE_ENC0_CLK_REG_FACTOR_M_OFFSET 0
  #define VE_ENC0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define VE_ENC1_CLK_REG 0x00000a84 //VE_ENC1 Clock Register
  #define VE_ENC1_CLK_REG_VE_ENC1_CLK_GATING_OFFSET 31
  #define VE_ENC1_CLK_REG_VE_ENC1_CLK_GATING_CLEAR_MASK (0x80000000)
    #define VE_ENC1_CLK_REG_VE_ENC1_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define VE_ENC1_CLK_REG_VE_ENC1_CLK_GATING_CLOCK_IS_ON (0b1)
  #define VE_ENC1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define VE_ENC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define VE_ENC1_CLK_REG_CLK_SRC_SEL_VE0PLL (0b000)
    #define VE_ENC1_CLK_REG_CLK_SRC_SEL_VE1PLL (0b001)
    #define VE_ENC1_CLK_REG_CLK_SRC_SEL_PERI0_800M (0b010)
    #define VE_ENC1_CLK_REG_CLK_SRC_SEL_PERI0_600M (0b011)
    #define VE_ENC1_CLK_REG_CLK_SRC_SEL_PERI0_480M (0b100)
    #define VE_ENC1_CLK_REG_CLK_SRC_SEL_DEPLL3X (0b101)
    #define VE_ENC1_CLK_REG_CLK_SRC_SEL_NPUPLL (0b110)
  #define VE_ENC1_CLK_REG_FACTOR_M_OFFSET 0
  #define VE_ENC1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define VE_DEC_CLK_REG 0x00000a88 //VE_DEC Clock Register
  #define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_OFFSET 31
  #define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLEAR_MASK (0x80000000)
    #define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define VE_DEC_CLK_REG_VE_DEC_CLK_GATING_CLOCK_IS_ON (0b1)
  #define VE_DEC_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define VE_DEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define VE_DEC_CLK_REG_CLK_SRC_SEL_VE1PLL (0b000)
    #define VE_DEC_CLK_REG_CLK_SRC_SEL_VE0PLL (0b001)
    #define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_800M (0b010)
    #define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_600M (0b011)
    #define VE_DEC_CLK_REG_CLK_SRC_SEL_PERI0_480M (0b100)
    #define VE_DEC_CLK_REG_CLK_SRC_SEL_DEPLL3X (0b101)
    #define VE_DEC_CLK_REG_CLK_SRC_SEL_NPUPLL (0b110)
  #define VE_DEC_CLK_REG_FACTOR_M_OFFSET 0
  #define VE_DEC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define VE_BGR_REG 0x00000a8c //VE Bus Gating Reset Register
  #define VE_BGR_REG_VE_DEC_RST_OFFSET 18
  #define VE_BGR_REG_VE_DEC_RST_CLEAR_MASK (0x00040000)
    #define VE_BGR_REG_VE_DEC_RST_ASSERT (0b0)
    #define VE_BGR_REG_VE_DEC_RST_DE_ASSERT (0b1)
  #define VE_BGR_REG_VE_ENC1_RST_OFFSET 17
  #define VE_BGR_REG_VE_ENC1_RST_CLEAR_MASK (0x00020000)
    #define VE_BGR_REG_VE_ENC1_RST_ASSERT (0b0)
    #define VE_BGR_REG_VE_ENC1_RST_DE_ASSERT (0b1)
  #define VE_BGR_REG_VE_ENC0_RST_OFFSET 16
  #define VE_BGR_REG_VE_ENC0_RST_CLEAR_MASK (0x00010000)
    #define VE_BGR_REG_VE_ENC0_RST_ASSERT (0b0)
    #define VE_BGR_REG_VE_ENC0_RST_DE_ASSERT (0b1)
  #define VE_BGR_REG_VE_DEC_GATING_OFFSET 2
  #define VE_BGR_REG_VE_DEC_GATING_CLEAR_MASK (0x00000004)
    #define VE_BGR_REG_VE_DEC_GATING_MASK (0x0)
    #define VE_BGR_REG_VE_DEC_GATING_PASS (0b1)
  #define VE_BGR_REG_VE_ENC1_GATING_OFFSET 1
  #define VE_BGR_REG_VE_ENC1_GATING_CLEAR_MASK (0x00000002)
    #define VE_BGR_REG_VE_ENC1_GATING_MASK (0x0)
    #define VE_BGR_REG_VE_ENC1_GATING_PASS (0b1)
  #define VE_BGR_REG_VE_ENC0_GATING_OFFSET 0
  #define VE_BGR_REG_VE_ENC0_GATING_CLEAR_MASK (0x00000001)
    #define VE_BGR_REG_VE_ENC0_GATING_MASK (0x0)
    #define VE_BGR_REG_VE_ENC0_GATING_PASS (0b1)

#define CE_CLK_REG 0x00000ac0 //CE Clock Register
  #define CE_CLK_REG_CE_CLK_GATING_OFFSET 31
  #define CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK (0x80000000)
    #define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define CE_CLK_REG_CE_CLK_GATING_SECURE_DEBUG (0b1)
  #define CE_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define CE_CLK_REG_CLK_SRC_SEL_HOSC (0b000)
    #define CE_CLK_REG_CLK_SRC_SEL_PERI0_400M (0b001)
    #define CE_CLK_REG_CLK_SRC_SEL_PERI0_600M (0b010)
  #define CE_CLK_REG_FACTOR_M_OFFSET 0
  #define CE_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define CE_BGR_REG 0x00000ac4 //CE Bus Gating Reset Register
  #define CE_BGR_REG_CE_SYS_RST_OFFSET 17
  #define CE_BGR_REG_CE_SYS_RST_CLEAR_MASK (0x00020000)
    #define CE_BGR_REG_CE_SYS_RST_ASSERT (0b0)
    #define CE_BGR_REG_CE_SYS_RST_SECURE_DEBUG (0b1)
  #define CE_BGR_REG_CE_RST_OFFSET 16
  #define CE_BGR_REG_CE_RST_CLEAR_MASK (0x00010000)
    #define CE_BGR_REG_CE_RST_ASSERT (0b0)
    #define CE_BGR_REG_CE_RST_SECURE_DEBUG (0b1)
  #define CE_BGR_REG_CE_SYS_GATING_OFFSET 1
  #define CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK (0x00000002)
    #define CE_BGR_REG_CE_SYS_GATING_MASK (0x0)
    #define CE_BGR_REG_CE_SYS_GATING_SECURE_DEBUG (0b1)
  #define CE_BGR_REG_CE_GATING_OFFSET 0
  #define CE_BGR_REG_CE_GATING_CLEAR_MASK (0x00000001)
    #define CE_BGR_REG_CE_GATING_MASK (0x0)
    #define CE_BGR_REG_CE_GATING_SECURE_DEBUG (0b1)

#define NPU_CLK_REG 0x00000b00 //NPU Clock Register
  #define NPU_CLK_REG_NPU_CLK_GATING_OFFSET 31
  #define NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK (0x80000000)
    #define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON (0b1)
  #define NPU_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define NPU_CLK_REG_CLK_SRC_SEL_NPUPLL (0b000)
    #define NPU_CLK_REG_CLK_SRC_SEL_PERI0_800M (0b001)
    #define NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M (0b010)
    #define NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M (0b011)
    #define NPU_CLK_REG_CLK_SRC_SEL_CCIPLL (0b100)
    #define NPU_CLK_REG_CLK_SRC_SEL_VE0PLL (0b101)
    #define NPU_CLK_REG_CLK_SRC_SEL_VE1PLL (0b110)
    #define NPU_CLK_REG_CLK_SRC_SEL_DEPLL3X (0b111)
  #define NPU_CLK_REG_FACTOR_M_OFFSET 0
  #define NPU_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define NPU_BGR_REG 0x00000b04 //NPU Bus Gating Reset Register
  #define NPU_BGR_REG_NPU_SYS_RST_OFFSET 19
  #define NPU_BGR_REG_NPU_SYS_RST_CLEAR_MASK (0x00080000)
    #define NPU_BGR_REG_NPU_SYS_RST_ASSERT (0b0)
    #define NPU_BGR_REG_NPU_SYS_RST_DE_ASSERT (0b1)
  #define NPU_BGR_REG_NPU_AHB_RST_OFFSET 18
  #define NPU_BGR_REG_NPU_AHB_RST_CLEAR_MASK (0x00040000)
    #define NPU_BGR_REG_NPU_AHB_RST_ASSERT (0b0)
    #define NPU_BGR_REG_NPU_AHB_RST_DE_ASSERT (0b1)
  #define NPU_BGR_REG_NPU_AXI_RST_OFFSET 17
  #define NPU_BGR_REG_NPU_AXI_RST_CLEAR_MASK (0x00020000)
    #define NPU_BGR_REG_NPU_AXI_RST_ASSERT (0b0)
    #define NPU_BGR_REG_NPU_AXI_RST_DE_ASSERT (0b1)
  #define NPU_BGR_REG_NPU_CORE_RST_OFFSET 16
  #define NPU_BGR_REG_NPU_CORE_RST_CLEAR_MASK (0x00010000)
    #define NPU_BGR_REG_NPU_CORE_RST_ASSERT (0b0)
    #define NPU_BGR_REG_NPU_CORE_RST_DE_ASSERT (0b1)
  #define NPU_BGR_REG_NPU_GATING_OFFSET 0
  #define NPU_BGR_REG_NPU_GATING_CLEAR_MASK (0x00000001)
    #define NPU_BGR_REG_NPU_GATING_MASK (0x0)
    #define NPU_BGR_REG_NPU_GATING_PASS (0b1)

#define AIPU_CLK_REG 0x00000b08 //AIPU Clock Register
  #define AIPU_CLK_REG_AIPU_CLK_GATING_OFFSET 31
  #define AIPU_CLK_REG_AIPU_CLK_GATING_CLEAR_MASK (0x80000000)
    #define AIPU_CLK_REG_AIPU_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define AIPU_CLK_REG_AIPU_CLK_GATING_CLOCK_IS_ON (0b1)
  #define AIPU_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define AIPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define AIPU_CLK_REG_CLK_SRC_SEL_PERI0_600M (0b000)
    #define AIPU_CLK_REG_CLK_SRC_SEL_PERI0_480M (0b001)
    #define AIPU_CLK_REG_CLK_SRC_SEL_PERI0_800M (0b010)
    #define AIPU_CLK_REG_CLK_SRC_SEL_NPUPLL (0b011)
    #define AIPU_CLK_REG_CLK_SRC_SEL_CCIPLL (0b100)
    #define AIPU_CLK_REG_CLK_SRC_SEL_VE0PLL (0b101)
    #define AIPU_CLK_REG_CLK_SRC_SEL_VE1PLL (0b110)
    #define AIPU_CLK_REG_CLK_SRC_SEL_DEPLL3X (0b111)
  #define AIPU_CLK_REG_FACTOR_M_OFFSET 0
  #define AIPU_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define AIPU_BGR_REG 0x00000b0c //AIPU Bus Gating Reset Register
  #define AIPU_BGR_REG_AIPU_CORE_RST_OFFSET 17
  #define AIPU_BGR_REG_AIPU_CORE_RST_CLEAR_MASK (0x00020000)
    #define AIPU_BGR_REG_AIPU_CORE_RST_ASSERT (0b0)
    #define AIPU_BGR_REG_AIPU_CORE_RST_DE_ASSERT (0b1)
  #define AIPU_BGR_REG_AIPU_RST_OFFSET 16
  #define AIPU_BGR_REG_AIPU_RST_CLEAR_MASK (0x00010000)
    #define AIPU_BGR_REG_AIPU_RST_ASSERT (0b0)
    #define AIPU_BGR_REG_AIPU_RST_DE_ASSERT (0b1)
  #define AIPU_BGR_REG_AIPU_GATING_OFFSET 0
  #define AIPU_BGR_REG_AIPU_GATING_CLEAR_MASK (0x00000001)
    #define AIPU_BGR_REG_AIPU_GATING_MASK (0x0)
    #define AIPU_BGR_REG_AIPU_GATING_PASS (0b1)

#define GPU0_CLK_REG 0x00000b20 //GPU0 Clock Register
  #define GPU0_CLK_REG_GPU0_CLK_GATING_OFFSET 31
  #define GPU0_CLK_REG_GPU0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define GPU0_CLK_REG_GPU0_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define GPU0_CLK_REG_GPU0_CLK_GATING_CLOCK_IS_ON (0b1)
  #define GPU0_CLK_REG_GPU0_UPD_OFFSET 27
  #define GPU0_CLK_REG_GPU0_UPD_CLEAR_MASK (0x08000000)
    #define GPU0_CLK_REG_GPU0_UPD_INVALID (0b0)
    #define GPU0_CLK_REG_GPU0_UPD_VALID (0b1)
  #define GPU0_CLK_REG_GPU0_CLK_SEL_OFFSET 24
  #define GPU0_CLK_REG_GPU0_CLK_SEL_CLEAR_MASK (0x07000000)
    #define GPU0_CLK_REG_GPU0_CLK_SEL_GPUPLL (0b000)
    #define GPU0_CLK_REG_GPU0_CLK_SEL_PERI0_800M (0b001)
    #define GPU0_CLK_REG_GPU0_CLK_SEL_PERI0_600M (0b010)
    #define GPU0_CLK_REG_GPU0_CLK_SEL_PERI0_400M (0b011)
    #define GPU0_CLK_REG_GPU0_CLK_SEL_PERI0_300M (0b100)
    #define GPU0_CLK_REG_GPU0_CLK_SEL_PERI0_200M (0b101)
  #define GPU0_CLK_REG_GPU0_DIV1_OFFSET 0
  #define GPU0_CLK_REG_GPU0_DIV1_CLEAR_MASK (0x0000000f)
    #define GPU0_CLK_REG_GPU0_DIV1_NOT_MASK (0x0000)
    #define GPU0_CLK_REG_GPU0_DIV1_MASK_1_CYCLE_AT_16_CYCLES (0b0001)
    #define GPU0_CLK_REG_GPU0_DIV1_MASK_2_CYCLES_AT_16_CYCLES (0b0010)
    #define GPU0_CLK_REG_GPU0_DIV1_MASK_3_CYCLES_AT_16_CYCLES (0b0011)
    #define GPU0_CLK_REG_GPU0_DIV1_MASK_15_CYCLES_AT_16_CYCLES (0b1111)

#define GPU0_GATING_REG 0x00000b24 //GPU0 Gating Reset Configuration Register
  #define GPU0_GATING_REG_GPU0_RST_OFFSET 16
  #define GPU0_GATING_REG_GPU0_RST_CLEAR_MASK (0x00010000)
    #define GPU0_GATING_REG_GPU0_RST_ASSERT (0b0)
    #define GPU0_GATING_REG_GPU0_RST_DE_ASSERT (0b1)
  #define GPU0_GATING_REG_GPU0_GATING_OFFSET 0
  #define GPU0_GATING_REG_GPU0_GATING_CLEAR_MASK (0x00000001)
    #define GPU0_GATING_REG_GPU0_GATING_MASK (0x0)
    #define GPU0_GATING_REG_GPU0_GATING_PASS (0b1)

#define DSP_CLK_REG 0x00000b40 //DSP Clock Register
  #define DSP_CLK_REG_DSP_CLK_GATING_OFFSET 31
  #define DSP_CLK_REG_DSP_CLK_GATING_CLEAR_MASK (0x80000000)
    #define DSP_CLK_REG_DSP_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define DSP_CLK_REG_DSP_CLK_GATING_CLOCK_IS_ON (0b1)
  #define DSP_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define DSP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define DSP_CLK_REG_CLK_SRC_SEL_HOSC (0b000)
    #define DSP_CLK_REG_CLK_SRC_SEL_CLK32K (0b001)
    #define DSP_CLK_REG_CLK_SRC_SEL_CLK16M_RC (0b010)
    #define DSP_CLK_REG_CLK_SRC_SEL_PERI0PLL2X (0b011)
    #define DSP_CLK_REG_CLK_SRC_SEL_PERI0_480M (0b100)
  #define DSP_CLK_REG_FACTOR_M_OFFSET 0
  #define DSP_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define DRAM0_CLK_REG 0x00000c00 //DRAM0 Clock Register
  #define DRAM0_CLK_REG_DRAM0_CLK_GATING_OFFSET 31
  #define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define DRAM0_CLK_REG_DRAM0_CLK_GATING_CLOCK_IS_ON (0b1)
  #define DRAM0_CLK_REG_DRAM0_UPD_OFFSET 27
  #define DRAM0_CLK_REG_DRAM0_UPD_CLEAR_MASK (0x08000000)
    #define DRAM0_CLK_REG_DRAM0_UPD_INVALID (0b0)
    #define DRAM0_CLK_REG_DRAM0_UPD_VALID (0b1)
  #define DRAM0_CLK_REG_DRAM0_CLK_SEL_OFFSET 24
  #define DRAM0_CLK_REG_DRAM0_CLK_SEL_CLEAR_MASK (0x07000000)
    #define DRAM0_CLK_REG_DRAM0_CLK_SEL_DDRPLL (0b000)
    #define DRAM0_CLK_REG_DRAM0_CLK_SEL_PERI1_800M (0b001)
    #define DRAM0_CLK_REG_DRAM0_CLK_SEL_PERI1_600M (0b010)
    #define DRAM0_CLK_REG_DRAM0_CLK_SEL_CCIPLL (0b011)
    #define DRAM0_CLK_REG_DRAM0_CLK_SEL_DEPLL3X (0b100)
    #define DRAM0_CLK_REG_DRAM0_CLK_SEL_NPUPLL (0b101)
  #define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_OFFSET 16
  #define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_CLEAR_MASK (0x00010000)
    #define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_FROM_PHY (0b0)
    #define DRAM0_CLK_REG_DRAM0_DDRCLK_SEL_DRAM0_CLK_4 (0b1)
  #define DRAM0_CLK_REG_DRAM0_DIV1_OFFSET 0
  #define DRAM0_CLK_REG_DRAM0_DIV1_CLEAR_MASK (0x0000001f)

#define DRAM_BGR_REG 0x00000c0c //DRAM Bus Gating Reset Register
  #define DRAM_BGR_REG_DRAM0_RST_OFFSET 16
  #define DRAM_BGR_REG_DRAM0_RST_CLEAR_MASK (0x00010000)
    #define DRAM_BGR_REG_DRAM0_RST_ASSERT (0b0)
    #define DRAM_BGR_REG_DRAM0_RST_DE_ASSERT (0b1)
  #define DRAM_BGR_REG_DRAM0_GATING_OFFSET 0
  #define DRAM_BGR_REG_DRAM0_GATING_CLEAR_MASK (0x00000001)
    #define DRAM_BGR_REG_DRAM0_GATING_MASK (0x0)
    #define DRAM_BGR_REG_DRAM0_GATING_PASS (0b1)

#define NAND0_CLK0_CLK_REG 0x00000c80 //NAND0 CLK0 Clock register
  #define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_OFFSET 31
  #define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_ON (0b1)
  #define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_HOSC (0b000)
    #define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_400M (0b001)
    #define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b010)
    #define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_400M (0b011)
    #define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_300M (0b100)
  #define NAND0_CLK0_CLK_REG_FACTOR_M_OFFSET 0
  #define NAND0_CLK0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define NAND0_CLK1_CLK_REG 0x00000c84 //NAND0 CLK1 Clock Register
  #define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET 31
  #define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK (0x80000000)
    #define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON (0b1)
  #define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC (0b000)
    #define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M (0b001)
    #define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b010)
    #define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M (0b011)
    #define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M (0b100)
  #define NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET 0
  #define NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define NAND_BGR_REG 0x00000c8c //NAND Bus Gating Reset Register
  #define NAND_BGR_REG_NAND0_RST_OFFSET 16
  #define NAND_BGR_REG_NAND0_RST_CLEAR_MASK (0x00010000)
    #define NAND_BGR_REG_NAND0_RST_ASSERT (0b0)
    #define NAND_BGR_REG_NAND0_RST_DE_ASSERT (0b1)
  #define NAND_BGR_REG_NAND0_GATING_OFFSET 0
  #define NAND_BGR_REG_NAND0_GATING_CLEAR_MASK (0x00000001)
    #define NAND_BGR_REG_NAND0_GATING_MASK (0x0)
    #define NAND_BGR_REG_NAND0_GATING_PASS (0b1)

#define SMHC0_CLK_REG 0x00000d00 //SMHC0 Clock Register
  #define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET 31
  #define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON (0b1)
  #define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define SMHC0_CLK_REG_CLK_SRC_SEL_HOSC (0b000)
    #define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M (0b001)
    #define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b010)
    #define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M (0b011)
    #define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M (0b100)
  #define SMHC0_CLK_REG_FACTOR_N_OFFSET 8
  #define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define SMHC0_CLK_REG_FACTOR_M_OFFSET 0
  #define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define SMHC0_24M_CLK_REG 0x00000d04 //SMHC0_24M Clock Register
  #define SMHC0_24M_CLK_REG_SMHC0_24M_CLK_GATING_OFFSET 31
  #define SMHC0_24M_CLK_REG_SMHC0_24M_CLK_GATING_CLEAR_MASK (0x80000000)
    #define SMHC0_24M_CLK_REG_SMHC0_24M_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define SMHC0_24M_CLK_REG_SMHC0_24M_CLK_GATING_CLOCK_IS_ON (0b1)
  #define SMHC0_24M_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SMHC0_24M_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define SMHC0_24M_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define SMHC0_24M_CLK_REG_CLK_SRC_SEL_HOSC (0b001)

#define SMHC0_BGR_REG 0x00000d0c //SMHC0 Bus Gating Reset Register
  #define SMHC0_BGR_REG_SMHC0_RST_OFFSET 16
  #define SMHC0_BGR_REG_SMHC0_RST_CLEAR_MASK (0x00010000)
    #define SMHC0_BGR_REG_SMHC0_RST_ASSERT (0b0)
    #define SMHC0_BGR_REG_SMHC0_RST_DE_ASSERT (0b1)
  #define SMHC0_BGR_REG_SMHC0_GATING_OFFSET 0
  #define SMHC0_BGR_REG_SMHC0_GATING_CLEAR_MASK (0x00000001)
    #define SMHC0_BGR_REG_SMHC0_GATING_MASK (0x0)
    #define SMHC0_BGR_REG_SMHC0_GATING_PASS (0b1)

#define SMHC1_CLK_REG 0x00000d10 //SMHC1 Clock Register
  #define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET 31
  #define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK (0x80000000)
    #define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON (0b1)
  #define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define SMHC1_CLK_REG_CLK_SRC_SEL_HOSC (0b000)
    #define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M (0b001)
    #define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b010)
    #define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M (0b011)
    #define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M (0b100)
  #define SMHC1_CLK_REG_FACTOR_N_OFFSET 8
  #define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define SMHC1_CLK_REG_FACTOR_M_OFFSET 0
  #define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define SMHC1_BGR_REG 0x00000d1c //SMHC1 Bus Gating Reset Register
  #define SMHC1_BGR_REG_SMHC1_RST_OFFSET 16
  #define SMHC1_BGR_REG_SMHC1_RST_CLEAR_MASK (0x00010000)
    #define SMHC1_BGR_REG_SMHC1_RST_ASSERT (0b0)
    #define SMHC1_BGR_REG_SMHC1_RST_DE_ASSERT (0b1)
  #define SMHC1_BGR_REG_SMHC1_GATING_OFFSET 0
  #define SMHC1_BGR_REG_SMHC1_GATING_CLEAR_MASK (0x00000001)
    #define SMHC1_BGR_REG_SMHC1_GATING_MASK (0x0)
    #define SMHC1_BGR_REG_SMHC1_GATING_PASS (0b1)

#define SMHC2_CLK_REG 0x00000d20 //SMHC2 Clock Register
  #define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET 31
  #define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK (0x80000000)
    #define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON (0b1)
  #define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define SMHC2_CLK_REG_CLK_SRC_SEL_HOSC (0b000)
    #define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M (0b001)
    #define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M (0b010)
    #define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M (0b011)
    #define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M (0b100)
  #define SMHC2_CLK_REG_FACTOR_N_OFFSET 8
  #define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define SMHC2_CLK_REG_FACTOR_M_OFFSET 0
  #define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define SMHC2_24M_CLK_REG 0x00000d24 //SMHC2_24M Clock Register
  #define SMHC2_24M_CLK_REG_SMHC2_24M_CLK_GATING_OFFSET 31
  #define SMHC2_24M_CLK_REG_SMHC2_24M_CLK_GATING_CLEAR_MASK (0x80000000)
    #define SMHC2_24M_CLK_REG_SMHC2_24M_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define SMHC2_24M_CLK_REG_SMHC2_24M_CLK_GATING_CLOCK_IS_ON (0b1)
  #define SMHC2_24M_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SMHC2_24M_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define SMHC2_24M_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define SMHC2_24M_CLK_REG_CLK_SRC_SEL_HOSC (0b001)

#define SMHC2_BGR_REG 0x00000d2c //SMHC2 Bus Gating Reset Register
  #define SMHC2_BGR_REG_SMHC2_RST_OFFSET 16
  #define SMHC2_BGR_REG_SMHC2_RST_CLEAR_MASK (0x00010000)
    #define SMHC2_BGR_REG_SMHC2_RST_ASSERT (0b0)
    #define SMHC2_BGR_REG_SMHC2_RST_DE_ASSERT (0b1)
  #define SMHC2_BGR_REG_SMHC2_GATING_OFFSET 0
  #define SMHC2_BGR_REG_SMHC2_GATING_CLEAR_MASK (0x00000001)
    #define SMHC2_BGR_REG_SMHC2_GATING_MASK (0x0)
    #define SMHC2_BGR_REG_SMHC2_GATING_PASS (0b1)

#define SMHC3_CLK_REG 0x00000d30 //SMHC3 Clock Register
  #define SMHC3_CLK_REG_SMHC3_CLK_GATING_OFFSET 31
  #define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLEAR_MASK (0x80000000)
    #define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define SMHC3_CLK_REG_SMHC3_CLK_GATING_CLOCK_IS_ON (0b1)
  #define SMHC3_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SMHC3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define SMHC3_CLK_REG_CLK_SRC_SEL_HOSC (0b000)
    #define SMHC3_CLK_REG_CLK_SRC_SEL_PERI0_800M (0b001)
    #define SMHC3_CLK_REG_CLK_SRC_SEL_PERI0_600M (0b010)
    #define SMHC3_CLK_REG_CLK_SRC_SEL_PERI1_800M (0b011)
    #define SMHC3_CLK_REG_CLK_SRC_SEL_PERI1_600M (0b100)
  #define SMHC3_CLK_REG_FACTOR_N_OFFSET 8
  #define SMHC3_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define SMHC3_CLK_REG_FACTOR_M_OFFSET 0
  #define SMHC3_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define SMHC3_24M_CLK_REG 0x00000d34 //SMHC3_24M Clock Register
  #define SMHC3_24M_CLK_REG_SMHC3_24M_CLK_GATING_OFFSET 31
  #define SMHC3_24M_CLK_REG_SMHC3_24M_CLK_GATING_CLEAR_MASK (0x80000000)
    #define SMHC3_24M_CLK_REG_SMHC3_24M_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define SMHC3_24M_CLK_REG_SMHC3_24M_CLK_GATING_CLOCK_IS_ON (0b1)
  #define SMHC3_24M_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SMHC3_24M_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define SMHC3_24M_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define SMHC3_24M_CLK_REG_CLK_SRC_SEL_HOSC (0b001)

#define SMHC3_BGR_REG 0x00000d3c //SMHC3 Bus Gating Reset Register
  #define SMHC3_BGR_REG_SMHC3_RST_OFFSET 16
  #define SMHC3_BGR_REG_SMHC3_RST_CLEAR_MASK (0x00010000)
    #define SMHC3_BGR_REG_SMHC3_RST_ASSERT (0b0)
    #define SMHC3_BGR_REG_SMHC3_RST_DE_ASSERT (0b1)
  #define SMHC3_BGR_REG_SMHC3_GATING_OFFSET 0
  #define SMHC3_BGR_REG_SMHC3_GATING_CLEAR_MASK (0x00000001)
    #define SMHC3_BGR_REG_SMHC3_GATING_MASK (0x0)
    #define SMHC3_BGR_REG_SMHC3_GATING_PASS (0b1)

#define UFS_AXI_CLK_REG 0x00000d80 //UFS_AXI Clock Register
  #define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_OFFSET 31
  #define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLEAR_MASK (0x80000000)
    #define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define UFS_AXI_CLK_REG_UFS_AXI_CLK_GATING_CLOCK_IS_ON (0b1)
  #define UFS_AXI_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define UFS_AXI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define UFS_AXI_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b000)
    #define UFS_AXI_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b001)
  #define UFS_AXI_CLK_REG_FACTOR_M_OFFSET 0
  #define UFS_AXI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define UFS_BGR_REG 0x00000d8c //UFS Bus Gating Reset Register
  #define UFS_BGR_REG_UFS_AXI_RST_OFFSET 17
  #define UFS_BGR_REG_UFS_AXI_RST_CLEAR_MASK (0x00020000)
    #define UFS_BGR_REG_UFS_AXI_RST_ASSERT (0b0)
    #define UFS_BGR_REG_UFS_AXI_RST_DE_ASSERT (0b1)
  #define UFS_BGR_REG_UFS_RST_OFFSET 16
  #define UFS_BGR_REG_UFS_RST_CLEAR_MASK (0x00010000)
    #define UFS_BGR_REG_UFS_RST_ASSERT (0b0)
    #define UFS_BGR_REG_UFS_RST_DE_ASSERT (0b1)
  #define UFS_BGR_REG_UFS_GATING_OFFSET 0
  #define UFS_BGR_REG_UFS_GATING_CLEAR_MASK (0x00000001)
    #define UFS_BGR_REG_UFS_GATING_MASK (0x0)
    #define UFS_BGR_REG_UFS_GATING_PASS (0b1)

#define UART0_BGR_REG 0x00000e00 //UART0 Bus Gating Reset Register
  #define UART0_BGR_REG_UART0_RST_OFFSET 16
  #define UART0_BGR_REG_UART0_RST_CLEAR_MASK (0x00010000)
    #define UART0_BGR_REG_UART0_RST_ASSERT (0b0)
    #define UART0_BGR_REG_UART0_RST_DE_ASSERT (0b1)
  #define UART0_BGR_REG_UART0_GATING_OFFSET 0
  #define UART0_BGR_REG_UART0_GATING_CLEAR_MASK (0x00000001)
    #define UART0_BGR_REG_UART0_GATING_MASK (0x0)
    #define UART0_BGR_REG_UART0_GATING_PASS (0b1)

#define UART1_BGR_REG 0x00000e04 //UART1 Bus Gating Reset Register
  #define UART1_BGR_REG_UART1_RST_OFFSET 16
  #define UART1_BGR_REG_UART1_RST_CLEAR_MASK (0x00010000)
    #define UART1_BGR_REG_UART1_RST_ASSERT (0b0)
    #define UART1_BGR_REG_UART1_RST_DE_ASSERT (0b1)
  #define UART1_BGR_REG_UART1_GATING_OFFSET 0
  #define UART1_BGR_REG_UART1_GATING_CLEAR_MASK (0x00000001)
    #define UART1_BGR_REG_UART1_GATING_MASK (0x0)
    #define UART1_BGR_REG_UART1_GATING_PASS (0b1)

#define UART2_BGR_REG 0x00000e08 //UART2 Bus Gating Reset Register
  #define UART2_BGR_REG_UART2_RST_OFFSET 16
  #define UART2_BGR_REG_UART2_RST_CLEAR_MASK (0x00010000)
    #define UART2_BGR_REG_UART2_RST_ASSERT (0b0)
    #define UART2_BGR_REG_UART2_RST_DE_ASSERT (0b1)
  #define UART2_BGR_REG_UART2_GATING_OFFSET 0
  #define UART2_BGR_REG_UART2_GATING_CLEAR_MASK (0x00000001)
    #define UART2_BGR_REG_UART2_GATING_MASK (0x0)
    #define UART2_BGR_REG_UART2_GATING_PASS (0b1)

#define UART3_BGR_REG 0x00000e0c //UART3 Bus Gating Reset Register
  #define UART3_BGR_REG_UART3_RST_OFFSET 16
  #define UART3_BGR_REG_UART3_RST_CLEAR_MASK (0x00010000)
    #define UART3_BGR_REG_UART3_RST_ASSERT (0b0)
    #define UART3_BGR_REG_UART3_RST_DE_ASSERT (0b1)
  #define UART3_BGR_REG_UART3_GATING_OFFSET 0
  #define UART3_BGR_REG_UART3_GATING_CLEAR_MASK (0x00000001)
    #define UART3_BGR_REG_UART3_GATING_MASK (0x0)
    #define UART3_BGR_REG_UART3_GATING_PASS (0b1)

#define UART4_BGR_REG 0x00000e10 //UART4 Bus Gating Reset Register
  #define UART4_BGR_REG_UART4_RST_OFFSET 16
  #define UART4_BGR_REG_UART4_RST_CLEAR_MASK (0x00010000)
    #define UART4_BGR_REG_UART4_RST_ASSERT (0b0)
    #define UART4_BGR_REG_UART4_RST_DE_ASSERT (0b1)
  #define UART4_BGR_REG_UART4_GATING_OFFSET 0
  #define UART4_BGR_REG_UART4_GATING_CLEAR_MASK (0x00000001)
    #define UART4_BGR_REG_UART4_GATING_MASK (0x0)
    #define UART4_BGR_REG_UART4_GATING_PASS (0b1)

#define UART5_BGR_REG 0x00000e14 //UART5 Bus Gating Reset Register
  #define UART5_BGR_REG_UART5_RST_OFFSET 16
  #define UART5_BGR_REG_UART5_RST_CLEAR_MASK (0x00010000)
    #define UART5_BGR_REG_UART5_RST_ASSERT (0b0)
    #define UART5_BGR_REG_UART5_RST_DE_ASSERT (0b1)
  #define UART5_BGR_REG_UART5_GATING_OFFSET 0
  #define UART5_BGR_REG_UART5_GATING_CLEAR_MASK (0x00000001)
    #define UART5_BGR_REG_UART5_GATING_MASK (0x0)
    #define UART5_BGR_REG_UART5_GATING_PASS (0b1)

#define UART6_BGR_REG 0x00000e18 //UART6 Bus Gating Reset Register
  #define UART6_BGR_REG_UART6_RST_OFFSET 16
  #define UART6_BGR_REG_UART6_RST_CLEAR_MASK (0x00010000)
    #define UART6_BGR_REG_UART6_RST_ASSERT (0b0)
    #define UART6_BGR_REG_UART6_RST_DE_ASSERT (0b1)
  #define UART6_BGR_REG_UART6_GATING_OFFSET 0
  #define UART6_BGR_REG_UART6_GATING_CLEAR_MASK (0x00000001)
    #define UART6_BGR_REG_UART6_GATING_MASK (0x0)
    #define UART6_BGR_REG_UART6_GATING_PASS (0b1)

#define UART7_BGR_REG 0x00000e1c //UART7 Bus Gating Reset Register
  #define UART7_BGR_REG_UART7_RST_OFFSET 16
  #define UART7_BGR_REG_UART7_RST_CLEAR_MASK (0x00010000)
    #define UART7_BGR_REG_UART7_RST_ASSERT (0b0)
    #define UART7_BGR_REG_UART7_RST_DE_ASSERT (0b1)
  #define UART7_BGR_REG_UART7_GATING_OFFSET 0
  #define UART7_BGR_REG_UART7_GATING_CLEAR_MASK (0x00000001)
    #define UART7_BGR_REG_UART7_GATING_MASK (0x0)
    #define UART7_BGR_REG_UART7_GATING_PASS (0b1)

#define UART8_BGR_REG 0x00000e20 //UART8 Bus Gating Reset Register
  #define UART8_BGR_REG_UART8_RST_OFFSET 16
  #define UART8_BGR_REG_UART8_RST_CLEAR_MASK (0x00010000)
    #define UART8_BGR_REG_UART8_RST_ASSERT (0b0)
    #define UART8_BGR_REG_UART8_RST_DE_ASSERT (0b1)
  #define UART8_BGR_REG_UART8_GATING_OFFSET 0
  #define UART8_BGR_REG_UART8_GATING_CLEAR_MASK (0x00000001)
    #define UART8_BGR_REG_UART8_GATING_MASK (0x0)
    #define UART8_BGR_REG_UART8_GATING_PASS (0b1)

#define TWI0_BGR_REG 0x00000e80 //TWI0 Bus Gating Reset Register
  #define TWI0_BGR_REG_TWI0_RST_OFFSET 16
  #define TWI0_BGR_REG_TWI0_RST_CLEAR_MASK (0x00010000)
    #define TWI0_BGR_REG_TWI0_RST_ASSERT (0b0)
    #define TWI0_BGR_REG_TWI0_RST_DE_ASSERT (0b1)
  #define TWI0_BGR_REG_TWI0_GATING_OFFSET 0
  #define TWI0_BGR_REG_TWI0_GATING_CLEAR_MASK (0x00000001)
    #define TWI0_BGR_REG_TWI0_GATING_MASK (0x0)
    #define TWI0_BGR_REG_TWI0_GATING_PASS (0b1)

#define TWI1_BGR_REG 0x00000e84 //TWI1 Bus Gating Reset Register
  #define TWI1_BGR_REG_TWI1_RST_OFFSET 16
  #define TWI1_BGR_REG_TWI1_RST_CLEAR_MASK (0x00010000)
    #define TWI1_BGR_REG_TWI1_RST_ASSERT (0b0)
    #define TWI1_BGR_REG_TWI1_RST_DE_ASSERT (0b1)
  #define TWI1_BGR_REG_TWI1_GATING_OFFSET 0
  #define TWI1_BGR_REG_TWI1_GATING_CLEAR_MASK (0x00000001)
    #define TWI1_BGR_REG_TWI1_GATING_MASK (0x0)
    #define TWI1_BGR_REG_TWI1_GATING_PASS (0b1)

#define TWI2_BGR_REG 0x00000e88 //TWI2 Bus Gating Reset Register
  #define TWI2_BGR_REG_TWI2_RST_OFFSET 16
  #define TWI2_BGR_REG_TWI2_RST_CLEAR_MASK (0x00010000)
    #define TWI2_BGR_REG_TWI2_RST_ASSERT (0b0)
    #define TWI2_BGR_REG_TWI2_RST_DE_ASSERT (0b1)
  #define TWI2_BGR_REG_TWI2_GATING_OFFSET 0
  #define TWI2_BGR_REG_TWI2_GATING_CLEAR_MASK (0x00000001)
    #define TWI2_BGR_REG_TWI2_GATING_MASK (0x0)
    #define TWI2_BGR_REG_TWI2_GATING_PASS (0b1)

#define TWI3_BGR_REG 0x00000e8c //TWI3 Bus Gating Reset Register
  #define TWI3_BGR_REG_TWI3_RST_OFFSET 16
  #define TWI3_BGR_REG_TWI3_RST_CLEAR_MASK (0x00010000)
    #define TWI3_BGR_REG_TWI3_RST_ASSERT (0b0)
    #define TWI3_BGR_REG_TWI3_RST_DE_ASSERT (0b1)
  #define TWI3_BGR_REG_TWI3_GATING_OFFSET 0
  #define TWI3_BGR_REG_TWI3_GATING_CLEAR_MASK (0x00000001)
    #define TWI3_BGR_REG_TWI3_GATING_MASK (0x0)
    #define TWI3_BGR_REG_TWI3_GATING_PASS (0b1)

#define TWI4_BGR_REG 0x00000e90 //TWI4 Bus Gating Reset Register
  #define TWI4_BGR_REG_TWI4_RST_OFFSET 16
  #define TWI4_BGR_REG_TWI4_RST_CLEAR_MASK (0x00010000)
    #define TWI4_BGR_REG_TWI4_RST_ASSERT (0b0)
    #define TWI4_BGR_REG_TWI4_RST_DE_ASSERT (0b1)
  #define TWI4_BGR_REG_TWI4_GATING_OFFSET 0
  #define TWI4_BGR_REG_TWI4_GATING_CLEAR_MASK (0x00000001)
    #define TWI4_BGR_REG_TWI4_GATING_MASK (0x0)
    #define TWI4_BGR_REG_TWI4_GATING_PASS (0b1)

#define TWI5_BGR_REG 0x00000e94 //TWI5 Bus Gating Reset Register
  #define TWI5_BGR_REG_TWI5_RST_OFFSET 16
  #define TWI5_BGR_REG_TWI5_RST_CLEAR_MASK (0x00010000)
    #define TWI5_BGR_REG_TWI5_RST_ASSERT (0b0)
    #define TWI5_BGR_REG_TWI5_RST_DE_ASSERT (0b1)
  #define TWI5_BGR_REG_TWI5_GATING_OFFSET 0
  #define TWI5_BGR_REG_TWI5_GATING_CLEAR_MASK (0x00000001)
    #define TWI5_BGR_REG_TWI5_GATING_MASK (0x0)
    #define TWI5_BGR_REG_TWI5_GATING_PASS (0b1)

#define TWI6_BGR_REG 0x00000e98 //TWI6 Bus Gating Reset Register
  #define TWI6_BGR_REG_TWI6_RST_OFFSET 16
  #define TWI6_BGR_REG_TWI6_RST_CLEAR_MASK (0x00010000)
    #define TWI6_BGR_REG_TWI6_RST_ASSERT (0b0)
    #define TWI6_BGR_REG_TWI6_RST_DE_ASSERT (0b1)
  #define TWI6_BGR_REG_TWI6_GATING_OFFSET 0
  #define TWI6_BGR_REG_TWI6_GATING_CLEAR_MASK (0x00000001)
    #define TWI6_BGR_REG_TWI6_GATING_MASK (0x0)
    #define TWI6_BGR_REG_TWI6_GATING_PASS (0b1)

#define TWI7_BGR_REG 0x00000e9c //TWI7 Bus Gating Reset Register
  #define TWI7_BGR_REG_TWI7_RST_OFFSET 16
  #define TWI7_BGR_REG_TWI7_RST_CLEAR_MASK (0x00010000)
    #define TWI7_BGR_REG_TWI7_RST_ASSERT (0b0)
    #define TWI7_BGR_REG_TWI7_RST_DE_ASSERT (0b1)
  #define TWI7_BGR_REG_TWI7_GATING_OFFSET 0
  #define TWI7_BGR_REG_TWI7_GATING_CLEAR_MASK (0x00000001)
    #define TWI7_BGR_REG_TWI7_GATING_MASK (0x0)
    #define TWI7_BGR_REG_TWI7_GATING_PASS (0b1)

#define TWI8_BGR_REG 0x00000ea0 //TWI8 Bus Gating Reset Register
  #define TWI8_BGR_REG_TWI8_RST_OFFSET 16
  #define TWI8_BGR_REG_TWI8_RST_CLEAR_MASK (0x00010000)
    #define TWI8_BGR_REG_TWI8_RST_ASSERT (0b0)
    #define TWI8_BGR_REG_TWI8_RST_DE_ASSERT (0b1)
  #define TWI8_BGR_REG_TWI8_GATING_OFFSET 0
  #define TWI8_BGR_REG_TWI8_GATING_CLEAR_MASK (0x00000001)
    #define TWI8_BGR_REG_TWI8_GATING_MASK (0x0)
    #define TWI8_BGR_REG_TWI8_GATING_PASS (0b1)

#define SPI0_CLK_REG 0x00000f00 //SPI0 Clock Register
  #define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET 31
  #define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON (0b1)
  #define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define SPI0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b001)
    #define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b010)
    #define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M (0b011)
    #define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M (0b100)
    #define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_160M (0b101)
    #define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_160M (0b110)
    #define SPI0_CLK_REG_CLK_SRC_SEL_HOSC (0b111)
  #define SPI0_CLK_REG_FACTOR_N_OFFSET 8
  #define SPI0_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define SPI0_CLK_REG_FACTOR_M_OFFSET 0
  #define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define SPI0_BGR_REG 0x00000f04 //SPI0 Bus Gating Reset Register
  #define SPI0_BGR_REG_SPI0_RST_OFFSET 16
  #define SPI0_BGR_REG_SPI0_RST_CLEAR_MASK (0x00010000)
    #define SPI0_BGR_REG_SPI0_RST_ASSERT (0b0)
    #define SPI0_BGR_REG_SPI0_RST_DE_ASSERT (0b1)
  #define SPI0_BGR_REG_SPI0_GATING_OFFSET 0
  #define SPI0_BGR_REG_SPI0_GATING_CLEAR_MASK (0x00000001)
    #define SPI0_BGR_REG_SPI0_GATING_MASK (0x0)
    #define SPI0_BGR_REG_SPI0_GATING_PASS (0b1)

#define SPI1_CLK_REG 0x00000f08 //SPI1 Clock Register
  #define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET 31
  #define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK (0x80000000)
    #define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON (0b1)
  #define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define SPI1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b001)
    #define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b010)
    #define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M (0b011)
    #define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M (0b100)
    #define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_160M (0b101)
    #define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_160M (0b110)
    #define SPI1_CLK_REG_CLK_SRC_SEL_HOSC (0b111)
  #define SPI1_CLK_REG_FACTOR_N_OFFSET 8
  #define SPI1_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define SPI1_CLK_REG_FACTOR_M_OFFSET 0
  #define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define SPI1_BGR_REG 0x00000f0c //SPI1 Bus Gating Reset Register
  #define SPI1_BGR_REG_SPI1_RST_OFFSET 16
  #define SPI1_BGR_REG_SPI1_RST_CLEAR_MASK (0x00010000)
    #define SPI1_BGR_REG_SPI1_RST_ASSERT (0b0)
    #define SPI1_BGR_REG_SPI1_RST_DE_ASSERT (0b1)
  #define SPI1_BGR_REG_SPI1_GATING_OFFSET 0
  #define SPI1_BGR_REG_SPI1_GATING_CLEAR_MASK (0x00000001)
    #define SPI1_BGR_REG_SPI1_GATING_MASK (0x0)
    #define SPI1_BGR_REG_SPI1_GATING_PASS (0b1)

#define SPI2_CLK_REG 0x00000f10 //SPI2 Clock Register
  #define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET 31
  #define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK (0x80000000)
    #define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON (0b1)
  #define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define SPI2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b001)
    #define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b010)
    #define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M (0b011)
    #define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M (0b100)
    #define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_160M (0b101)
    #define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_160M (0b110)
    #define SPI2_CLK_REG_CLK_SRC_SEL_HOSC (0b111)
  #define SPI2_CLK_REG_FACTOR_N_OFFSET 8
  #define SPI2_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define SPI2_CLK_REG_FACTOR_M_OFFSET 0
  #define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define SPI2_BGR_REG 0x00000f14 //SPI2 Bus Gating Reset Register
  #define SPI2_BGR_REG_SPI2_RST_OFFSET 16
  #define SPI2_BGR_REG_SPI2_RST_CLEAR_MASK (0x00010000)
    #define SPI2_BGR_REG_SPI2_RST_ASSERT (0b0)
    #define SPI2_BGR_REG_SPI2_RST_DE_ASSERT (0b1)
  #define SPI2_BGR_REG_SPI2_GATING_OFFSET 0
  #define SPI2_BGR_REG_SPI2_GATING_CLEAR_MASK (0x00000001)
    #define SPI2_BGR_REG_SPI2_GATING_MASK (0x0)
    #define SPI2_BGR_REG_SPI2_GATING_PASS (0b1)

#define SPIF_CLK_REG 0x00000f18 //SPIF Clock Register
  #define SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET 31
  #define SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK (0x80000000)
    #define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON (0b1)
  #define SPIF_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define SPIF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_400M (0b001)
    #define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b010)
    #define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_400M (0b011)
    #define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M (0b100)
    #define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_160M (0b101)
    #define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_160M (0b110)
    #define SPIF_CLK_REG_CLK_SRC_SEL_HOSC (0b111)
  #define SPIF_CLK_REG_FACTOR_N_OFFSET 8
  #define SPIF_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define SPIF_CLK_REG_FACTOR_M_OFFSET 0
  #define SPIF_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define SPIF_BGR_REG 0x00000f1c //SPIF Bus Gating Reset Register
  #define SPIF_BGR_REG_SPIF_RST_OFFSET 16
  #define SPIF_BGR_REG_SPIF_RST_CLEAR_MASK (0x00010000)
    #define SPIF_BGR_REG_SPIF_RST_ASSERT (0b0)
    #define SPIF_BGR_REG_SPIF_RST_DE_ASSERT (0b1)
  #define SPIF_BGR_REG_SPIF_GATING_OFFSET 0
  #define SPIF_BGR_REG_SPIF_GATING_CLEAR_MASK (0x00000001)
    #define SPIF_BGR_REG_SPIF_GATING_MASK (0x0)
    #define SPIF_BGR_REG_SPIF_GATING_PASS (0b1)

#define GPADC0_24M_CLK_REG 0x00000fc0 //GPADC0_24M Clock Register
  #define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_OFFSET 31
  #define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLEAR_MASK (0x80000000)
    #define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define GPADC0_24M_CLK_REG_GPADC0_24M_CLK_GATING_CLOCK_IS_ON (0b1)
  #define GPADC0_24M_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define GPADC0_24M_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define GPADC0_24M_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define GPADC0_24M_CLK_REG_CLK_SRC_SEL_HOSC (0b001)
  #define GPADC0_24M_CLK_REG_FACTOR_M_OFFSET 0
  #define GPADC0_24M_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define GPADC0_BGR_REG 0x00000fc4 //GPADC0 Bus Gating Reset Register
  #define GPADC0_BGR_REG_GPADC0_RST_OFFSET 16
  #define GPADC0_BGR_REG_GPADC0_RST_CLEAR_MASK (0x00010000)
    #define GPADC0_BGR_REG_GPADC0_RST_ASSERT (0b0)
    #define GPADC0_BGR_REG_GPADC0_RST_DE_ASSERT (0b1)
  #define GPADC0_BGR_REG_GPADC0_GATING_OFFSET 0
  #define GPADC0_BGR_REG_GPADC0_GATING_CLEAR_MASK (0x00000001)
    #define GPADC0_BGR_REG_GPADC0_GATING_MASK (0x0)
    #define GPADC0_BGR_REG_GPADC0_GATING_PASS (0b1)

#define GPADC1_24M_CLK_REG 0x00000fc8 //GPADC1_24M Clock Register
  #define GPADC1_24M_CLK_REG_GPADC1_24M_CLK_GATING_OFFSET 31
  #define GPADC1_24M_CLK_REG_GPADC1_24M_CLK_GATING_CLEAR_MASK (0x80000000)
    #define GPADC1_24M_CLK_REG_GPADC1_24M_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define GPADC1_24M_CLK_REG_GPADC1_24M_CLK_GATING_CLOCK_IS_ON (0b1)
  #define GPADC1_24M_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define GPADC1_24M_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define GPADC1_24M_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define GPADC1_24M_CLK_REG_CLK_SRC_SEL_HOSC (0b001)
  #define GPADC1_24M_CLK_REG_FACTOR_M_OFFSET 0
  #define GPADC1_24M_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define GPADC1_BGR_REG 0x00000fcc //GPADC1 Bus Gating Reset Register
  #define GPADC1_BGR_REG_GPADC1_RST_OFFSET 16
  #define GPADC1_BGR_REG_GPADC1_RST_CLEAR_MASK (0x00010000)
    #define GPADC1_BGR_REG_GPADC1_RST_ASSERT (0b0)
    #define GPADC1_BGR_REG_GPADC1_RST_DE_ASSERT (0b1)
  #define GPADC1_BGR_REG_GPADC1_GATING_OFFSET 0
  #define GPADC1_BGR_REG_GPADC1_GATING_CLEAR_MASK (0x00000001)
    #define GPADC1_BGR_REG_GPADC1_GATING_MASK (0x0)
    #define GPADC1_BGR_REG_GPADC1_GATING_PASS (0b1)

#define THS0_BGR_REG 0x00000fe4 //THS0 Bus Gating Reset Register
  #define THS0_BGR_REG_THS0_RST_OFFSET 16
  #define THS0_BGR_REG_THS0_RST_CLEAR_MASK (0x00010000)
    #define THS0_BGR_REG_THS0_RST_ASSERT (0b0)
    #define THS0_BGR_REG_THS0_RST_DE_ASSERT (0b1)
  #define THS0_BGR_REG_THS0_GATING_OFFSET 0
  #define THS0_BGR_REG_THS0_GATING_CLEAR_MASK (0x00000001)
    #define THS0_BGR_REG_THS0_GATING_MASK (0x0)
    #define THS0_BGR_REG_THS0_GATING_PASS (0b1)

#define IRRX_CLK_REG 0x00001000 //IRRX Clock register
  #define IRRX_CLK_REG_IRRX_CLK_GATING_OFFSET 31
  #define IRRX_CLK_REG_IRRX_CLK_GATING_CLEAR_MASK (0x80000000)
    #define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_ON (0b1)
  #define IRRX_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define IRRX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define IRRX_CLK_REG_CLK_SRC_SEL_CLK32K (0b000)
    #define IRRX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b001)
    #define IRRX_CLK_REG_CLK_SRC_SEL_HOSC (0b010)
  #define IRRX_CLK_REG_FACTOR_M_OFFSET 0
  #define IRRX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define IRRX_BGR_REG 0x00001004 //IRRX Bus Gating Reset Register
  #define IRRX_BGR_REG_IRRX_RST_OFFSET 16
  #define IRRX_BGR_REG_IRRX_RST_CLEAR_MASK (0x00010000)
    #define IRRX_BGR_REG_IRRX_RST_ASSERT (0b0)
    #define IRRX_BGR_REG_IRRX_RST_DE_ASSERT (0b1)
  #define IRRX_BGR_REG_IRRX_GATING_OFFSET 0
  #define IRRX_BGR_REG_IRRX_GATING_CLEAR_MASK (0x00000001)
    #define IRRX_BGR_REG_IRRX_GATING_MASK (0x0)
    #define IRRX_BGR_REG_IRRX_GATING_PASS (0b1)

#define IRTX_CLK_REG 0x00001008 //IRTX Clock register
  #define IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET 31
  #define IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK (0x80000000)
    #define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON (0b1)
  #define IRTX_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define IRTX_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M (0b001)
    #define IRTX_CLK_REG_CLK_SRC_SEL_HOSC (0b010)
  #define IRTX_CLK_REG_FACTOR_M_OFFSET 0
  #define IRTX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define IRTX_BGR_REG 0x0000100c //IRTX Bus Gating Reset Register
  #define IRTX_BGR_REG_IRTX_RST_OFFSET 16
  #define IRTX_BGR_REG_IRTX_RST_CLEAR_MASK (0x00010000)
    #define IRTX_BGR_REG_IRTX_RST_ASSERT (0b0)
    #define IRTX_BGR_REG_IRTX_RST_DE_ASSERT (0b1)
  #define IRTX_BGR_REG_IRTX_GATING_OFFSET 0
  #define IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK (0x00000001)
    #define IRTX_BGR_REG_IRTX_GATING_MASK (0x0)
    #define IRTX_BGR_REG_IRTX_GATING_PASS (0b1)

#define LRADC_BGR_REG 0x00001024 //LRADC Bus Gating Reset Register
  #define LRADC_BGR_REG_LRADC_RST_OFFSET 16
  #define LRADC_BGR_REG_LRADC_RST_CLEAR_MASK (0x00010000)
    #define LRADC_BGR_REG_LRADC_RST_ASSERT (0b0)
    #define LRADC_BGR_REG_LRADC_RST_DE_ASSERT (0b1)
  #define LRADC_BGR_REG_LRADC_GATING_OFFSET 0
  #define LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK (0x00000001)
    #define LRADC_BGR_REG_LRADC_GATING_MASK (0x0)
    #define LRADC_BGR_REG_LRADC_GATING_PASS (0b1)

#define LBC_CLK_REG 0x00001040 //LBC Clock Register
  #define LBC_CLK_REG_LBC_CLK_GATING_OFFSET 31
  #define LBC_CLK_REG_LBC_CLK_GATING_CLEAR_MASK (0x80000000)
    #define LBC_CLK_REG_LBC_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define LBC_CLK_REG_LBC_CLK_GATING_CLOCK_IS_ON (0b1)
  #define LBC_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define LBC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define LBC_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X (0b000)
    #define LBC_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X (0b001)
    #define LBC_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X (0b010)
    #define LBC_CLK_REG_CLK_SRC_SEL_VIDEO3PLL3X (0b011)
    #define LBC_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b100)
    #define LBC_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b101)
  #define LBC_CLK_REG_FACTOR_N_OFFSET 8
  #define LBC_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define LBC_CLK_REG_FACTOR_M_OFFSET 0
  #define LBC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define LBC_BGR_REG 0x00001044 //LBC Bus Gating Reset Register
  #define LBC_BGR_REG_LBC_RST_OFFSET 16
  #define LBC_BGR_REG_LBC_RST_CLEAR_MASK (0x00010000)
    #define LBC_BGR_REG_LBC_RST_ASSERT (0b0)
    #define LBC_BGR_REG_LBC_RST_DE_ASSERT (0b1)
  #define LBC_BGR_REG_LBC_GATING_OFFSET 0
  #define LBC_BGR_REG_LBC_GATING_CLEAR_MASK (0x00000001)
    #define LBC_BGR_REG_LBC_GATING_MASK (0x0)
    #define LBC_BGR_REG_LBC_GATING_PASS (0b1)

#define I2SPCM1_CLK_REG 0x00001210 //I2SPCM1 Clock Register
  #define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_OFFSET 31
  #define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLEAR_MASK (0x80000000)
    #define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define I2SPCM1_CLK_REG_I2SPCM1_CLK_GATING_CLOCK_IS_ON (0b1)
  #define I2SPCM1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define I2SPCM1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X (0b000)
    #define I2SPCM1_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X (0b001)
    #define I2SPCM1_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b010)
  #define I2SPCM1_CLK_REG_FACTOR_M_OFFSET 0
  #define I2SPCM1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define I2SPCM1_BGR_REG 0x0000121c //I2SPCM1 Bus Gating Reset Register
  #define I2SPCM1_BGR_REG_I2SPCM1_RST_OFFSET 16
  #define I2SPCM1_BGR_REG_I2SPCM1_RST_CLEAR_MASK (0x00010000)
    #define I2SPCM1_BGR_REG_I2SPCM1_RST_ASSERT (0b0)
    #define I2SPCM1_BGR_REG_I2SPCM1_RST_DE_ASSERT (0b1)
  #define I2SPCM1_BGR_REG_I2SPCM1_GATING_OFFSET 0
  #define I2SPCM1_BGR_REG_I2SPCM1_GATING_CLEAR_MASK (0x00000001)
    #define I2SPCM1_BGR_REG_I2SPCM1_GATING_MASK (0x0)
    #define I2SPCM1_BGR_REG_I2SPCM1_GATING_PASS (0b1)

#define I2SPCM2_CLK_REG 0x00001220 //I2SPCM2 Clock Register
  #define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_OFFSET 31
  #define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLEAR_MASK (0x80000000)
    #define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define I2SPCM2_CLK_REG_I2SPCM2_CLK_GATING_CLOCK_IS_ON (0b1)
  #define I2SPCM2_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define I2SPCM2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X (0b000)
    #define I2SPCM2_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X (0b001)
    #define I2SPCM2_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b010)
  #define I2SPCM2_CLK_REG_FACTOR_M_OFFSET 0
  #define I2SPCM2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define I2SPCM2_ASRC_CLK_REG 0x00001224 //I2SPCM2_ASRC Clock Register
  #define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_OFFSET 31
  #define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLEAR_MASK (0x80000000)
    #define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define I2SPCM2_ASRC_CLK_REG_I2SPCM2_ASRC_CLK_GATING_CLOCK_IS_ON (0b1)
  #define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X (0b000)
    #define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X (0b001)
    #define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b010)
    #define I2SPCM2_ASRC_CLK_REG_CLK_SRC_SEL_PERI1_300M (0b011)
  #define I2SPCM2_ASRC_CLK_REG_FACTOR_M_OFFSET 0
  #define I2SPCM2_ASRC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define I2SPCM2_BGR_REG 0x0000122c //I2SPCM2 Bus Gating Reset Register
  #define I2SPCM2_BGR_REG_I2SPCM2_RST_OFFSET 16
  #define I2SPCM2_BGR_REG_I2SPCM2_RST_CLEAR_MASK (0x00010000)
    #define I2SPCM2_BGR_REG_I2SPCM2_RST_ASSERT (0b0)
    #define I2SPCM2_BGR_REG_I2SPCM2_RST_DE_ASSERT (0b1)
  #define I2SPCM2_BGR_REG_I2SPCM2_GATING_OFFSET 0
  #define I2SPCM2_BGR_REG_I2SPCM2_GATING_CLEAR_MASK (0x00000001)
    #define I2SPCM2_BGR_REG_I2SPCM2_GATING_MASK (0x0)
    #define I2SPCM2_BGR_REG_I2SPCM2_GATING_PASS (0b1)
    #define I2SPCM2_BGR_REG_I2SPCM2_GATING____CCU_AUTO_GEN_I2S2_PROT (0b2)

#define I2SPCM3_CLK_REG 0x00001230 //I2SPCM3 Clock Register
  #define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_OFFSET 31
  #define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLEAR_MASK (0x80000000)
    #define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define I2SPCM3_CLK_REG_I2SPCM3_CLK_GATING_CLOCK_IS_ON (0b1)
  #define I2SPCM3_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define I2SPCM3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X (0b000)
    #define I2SPCM3_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X (0b001)
    #define I2SPCM3_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b010)
  #define I2SPCM3_CLK_REG_FACTOR_M_OFFSET 0
  #define I2SPCM3_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define I2SPCM3_BGR_REG 0x0000123c //I2SPCM3 Bus Gating Reset Register
  #define I2SPCM3_BGR_REG_I2SPCM3_RST_OFFSET 16
  #define I2SPCM3_BGR_REG_I2SPCM3_RST_CLEAR_MASK (0x00010000)
    #define I2SPCM3_BGR_REG_I2SPCM3_RST_ASSERT (0b0)
    #define I2SPCM3_BGR_REG_I2SPCM3_RST_DE_ASSERT (0b1)
  #define I2SPCM3_BGR_REG_I2SPCM3_GATING_OFFSET 0
  #define I2SPCM3_BGR_REG_I2SPCM3_GATING_CLEAR_MASK (0x00000001)
    #define I2SPCM3_BGR_REG_I2SPCM3_GATING_MASK (0x0)
    #define I2SPCM3_BGR_REG_I2SPCM3_GATING_PASS (0b1)
    #define I2SPCM3_BGR_REG_I2SPCM3_GATING____CCU_AUTO_GEN_I2S3_PROT (0b3)

#define I2SPCM4_CLK_REG 0x00001240 //I2SPCM4 Clock Register
  #define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_OFFSET 31
  #define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLEAR_MASK (0x80000000)
    #define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define I2SPCM4_CLK_REG_I2SPCM4_CLK_GATING_CLOCK_IS_ON (0b1)
  #define I2SPCM4_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define I2SPCM4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X (0b000)
    #define I2SPCM4_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X (0b001)
    #define I2SPCM4_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b010)
  #define I2SPCM4_CLK_REG_FACTOR_M_OFFSET 0
  #define I2SPCM4_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define I2SPCM4_BGR_REG 0x0000124c //I2SPCM4 Bus Gating Reset Register
  #define I2SPCM4_BGR_REG_I2SPCM4_RST_OFFSET 16
  #define I2SPCM4_BGR_REG_I2SPCM4_RST_CLEAR_MASK (0x00010000)
    #define I2SPCM4_BGR_REG_I2SPCM4_RST_ASSERT (0b0)
    #define I2SPCM4_BGR_REG_I2SPCM4_RST_DE_ASSERT (0b1)
  #define I2SPCM4_BGR_REG_I2SPCM4_GATING_OFFSET 0
  #define I2SPCM4_BGR_REG_I2SPCM4_GATING_CLEAR_MASK (0x00000001)
    #define I2SPCM4_BGR_REG_I2SPCM4_GATING_MASK (0x0)
    #define I2SPCM4_BGR_REG_I2SPCM4_GATING_PASS (0b1)
    #define I2SPCM4_BGR_REG_I2SPCM4_GATING____CCU_AUTO_GEN_I2S4_PROT (0b4)

#define I2SPCM5_CLK_REG 0x00001250 //I2SPCM5 Clock Register
  #define I2SPCM5_CLK_REG_I2SPCM5_CLK_GATING_OFFSET 31
  #define I2SPCM5_CLK_REG_I2SPCM5_CLK_GATING_CLEAR_MASK (0x80000000)
    #define I2SPCM5_CLK_REG_I2SPCM5_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define I2SPCM5_CLK_REG_I2SPCM5_CLK_GATING_CLOCK_IS_ON (0b1)
  #define I2SPCM5_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define I2SPCM5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define I2SPCM5_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X (0b000)
    #define I2SPCM5_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X (0b001)
    #define I2SPCM5_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b010)
  #define I2SPCM5_CLK_REG_FACTOR_M_OFFSET 0
  #define I2SPCM5_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define I2SPCM5_BGR_REG 0x0000125c //I2SPCM5 Bus Gating Reset Register
  #define I2SPCM5_BGR_REG_I2SPCM5_RST_OFFSET 16
  #define I2SPCM5_BGR_REG_I2SPCM5_RST_CLEAR_MASK (0x00010000)
    #define I2SPCM5_BGR_REG_I2SPCM5_RST_ASSERT (0b0)
    #define I2SPCM5_BGR_REG_I2SPCM5_RST_DE_ASSERT (0b1)
  #define I2SPCM5_BGR_REG_I2SPCM5_GATING_OFFSET 0
  #define I2SPCM5_BGR_REG_I2SPCM5_GATING_CLEAR_MASK (0x00000001)
    #define I2SPCM5_BGR_REG_I2SPCM5_GATING_MASK (0x0)
    #define I2SPCM5_BGR_REG_I2SPCM5_GATING_PASS (0b1)
    #define I2SPCM5_BGR_REG_I2SPCM5_GATING____CCU_AUTO_GEN_I2S5_PROT (0b5)

#define SPDIF_TX_CLK_REG 0x00001280 //SPDIF TX Clock Register
  #define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_OFFSET 31
  #define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLEAR_MASK (0x80000000)
    #define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define SPDIF_TX_CLK_REG_SPDIF_TX_CLK_GATING_CLOCK_IS_ON (0b1)
  #define SPDIF_TX_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SPDIF_TX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO0PLL4X (0b000)
    #define SPDIF_TX_CLK_REG_CLK_SRC_SEL_AUDIO1PLL4X (0b001)
  #define SPDIF_TX_CLK_REG_FACTOR_M_OFFSET 0
  #define SPDIF_TX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define SPDIF_RX_CLK_REG 0x00001284 //SPDIF RX Clock Register
  #define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_OFFSET 31
  #define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLEAR_MASK (0x80000000)
    #define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define SPDIF_RX_CLK_REG_SPDIF_RX_CLK_GATING_CLOCK_IS_ON (0b1)
  #define SPDIF_RX_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SPDIF_RX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b000)
    #define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b001)
    #define SPDIF_RX_CLK_REG_CLK_SRC_SEL_PERI0_400M (0b010)
  #define SPDIF_RX_CLK_REG_FACTOR_M_OFFSET 0
  #define SPDIF_RX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define SPDIF_BGR_REG 0x0000128c //SPDIF Bus Gating Reset Register
  #define SPDIF_BGR_REG_SPDIF_RST_OFFSET 16
  #define SPDIF_BGR_REG_SPDIF_RST_CLEAR_MASK (0x00010000)
    #define SPDIF_BGR_REG_SPDIF_RST_ASSERT (0b0)
    #define SPDIF_BGR_REG_SPDIF_RST_DE_ASSERT (0b1)
  #define SPDIF_BGR_REG_SPDIF_GATING_OFFSET 0
  #define SPDIF_BGR_REG_SPDIF_GATING_CLEAR_MASK (0x00000001)
    #define SPDIF_BGR_REG_SPDIF_GATING_MASK (0x0)
    #define SPDIF_BGR_REG_SPDIF_GATING_PASS (0b1)

#define USB2_HOST0_CLK_REG 0x00001300 //USB2_HOST0 Clock Register
  #define USB2_HOST0_CLK_REG_USB2_HOST0_CLKEN_OFFSET 31
  #define USB2_HOST0_CLK_REG_USB2_HOST0_CLKEN_CLEAR_MASK (0x80000000)
    #define USB2_HOST0_CLK_REG_USB2_HOST0_CLKEN_CLOCK_IS_OFF (0b0)
    #define USB2_HOST0_CLK_REG_USB2_HOST0_CLKEN_CLOCK_IS_ON (0b1)
  #define USB2_HOST0_CLK_REG_USB2_PHY0_RSTN_OFFSET 30
  #define USB2_HOST0_CLK_REG_USB2_PHY0_RSTN_CLEAR_MASK (0x40000000)
    #define USB2_HOST0_CLK_REG_USB2_PHY0_RSTN_ASSERT (0b0)
    #define USB2_HOST0_CLK_REG_USB2_PHY0_RSTN_DE_ASSERT (0b1)
  #define USB2_HOST0_CLK_REG_USB2_HOST0_CLK12M_SEL_OFFSET 24
  #define USB2_HOST0_CLK_REG_USB2_HOST0_CLK12M_SEL_CLEAR_MASK (0x03000000)
    #define USB2_HOST0_CLK_REG_USB2_HOST0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ (0b000)
    #define USB2_HOST0_CLK_REG_USB2_HOST0_CLK12M_SEL_12M_DIVIDED_FROM_SYS_CLK24M (0b001)
    #define USB2_HOST0_CLK_REG_USB2_HOST0_CLK12M_SEL_CLK32K (0b010)
    #define USB2_HOST0_CLK_REG_USB2_HOST0_CLK12M_SEL_CLK16M_RC (0b011)

#define USB2_HOST0_BGR_REG 0x00001304 //USB2_HOST0 Bus Gating Reset Register
  #define USB2_HOST0_BGR_REG_USB2_OTG0_RST_OFFSET 24
  #define USB2_HOST0_BGR_REG_USB2_OTG0_RST_CLEAR_MASK (0x01000000)
    #define USB2_HOST0_BGR_REG_USB2_OTG0_RST_ASSERT (0b0)
    #define USB2_HOST0_BGR_REG_USB2_OTG0_RST_DE_ASSERT (0b1)
  #define USB2_HOST0_BGR_REG_USB2_EHCI0_RST_OFFSET 20
  #define USB2_HOST0_BGR_REG_USB2_EHCI0_RST_CLEAR_MASK (0x00100000)
    #define USB2_HOST0_BGR_REG_USB2_EHCI0_RST_ASSERT (0b0)
    #define USB2_HOST0_BGR_REG_USB2_EHCI0_RST_DE_ASSERT (0b1)
  #define USB2_HOST0_BGR_REG_USB2_OHCI0_RST_OFFSET 16
  #define USB2_HOST0_BGR_REG_USB2_OHCI0_RST_CLEAR_MASK (0x00010000)
    #define USB2_HOST0_BGR_REG_USB2_OHCI0_RST_ASSERT (0b0)
    #define USB2_HOST0_BGR_REG_USB2_OHCI0_RST_DE_ASSERT (0b1)
  #define USB2_HOST0_BGR_REG_USB2_OTG0_GATING_OFFSET 8
  #define USB2_HOST0_BGR_REG_USB2_OTG0_GATING_CLEAR_MASK (0x00000100)
    #define USB2_HOST0_BGR_REG_USB2_OTG0_GATING_MASK (0x0)
    #define USB2_HOST0_BGR_REG_USB2_OTG0_GATING_PASS (0b1)
  #define USB2_HOST0_BGR_REG_USB2_EHCI0_GATING_OFFSET 4
  #define USB2_HOST0_BGR_REG_USB2_EHCI0_GATING_CLEAR_MASK (0x00000010)
    #define USB2_HOST0_BGR_REG_USB2_EHCI0_GATING_MASK (0x0)
    #define USB2_HOST0_BGR_REG_USB2_EHCI0_GATING_PASS (0b1)
  #define USB2_HOST0_BGR_REG_USB2_OHCI0_GATING_OFFSET 0
  #define USB2_HOST0_BGR_REG_USB2_OHCI0_GATING_CLEAR_MASK (0x00000001)
    #define USB2_HOST0_BGR_REG_USB2_OHCI0_GATING_MASK (0x0)
    #define USB2_HOST0_BGR_REG_USB2_OHCI0_GATING_PASS (0b1)

#define USB2_HOST1_CLK_REG 0x00001308 //USB2_HOST1 Clock Register
  #define USB2_HOST1_CLK_REG_USB2_HOST1_CLKEN_OFFSET 31
  #define USB2_HOST1_CLK_REG_USB2_HOST1_CLKEN_CLEAR_MASK (0x80000000)
    #define USB2_HOST1_CLK_REG_USB2_HOST1_CLKEN_CLOCK_IS_OFF (0b0)
    #define USB2_HOST1_CLK_REG_USB2_HOST1_CLKEN_CLOCK_IS_ON (0b1)
  #define USB2_HOST1_CLK_REG_USB2_PHY1_RSTN_OFFSET 30
  #define USB2_HOST1_CLK_REG_USB2_PHY1_RSTN_CLEAR_MASK (0x40000000)
    #define USB2_HOST1_CLK_REG_USB2_PHY1_RSTN_ASSERT (0b0)
    #define USB2_HOST1_CLK_REG_USB2_PHY1_RSTN_DE_ASSERT (0b1)
  #define USB2_HOST1_CLK_REG_USB2_HOST1_CLK12M_SEL_OFFSET 24
  #define USB2_HOST1_CLK_REG_USB2_HOST1_CLK12M_SEL_CLEAR_MASK (0x03000000)
    #define USB2_HOST1_CLK_REG_USB2_HOST1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ (0b000)
    #define USB2_HOST1_CLK_REG_USB2_HOST1_CLK12M_SEL_12M_DIVIDED_FROM_SYS_CLK24M (0b001)
    #define USB2_HOST1_CLK_REG_USB2_HOST1_CLK12M_SEL_CLK32K (0b010)
    #define USB2_HOST1_CLK_REG_USB2_HOST1_CLK12M_SEL_CLK16M_RC (0b011)

#define USB2_HOST1_BGR_REG 0x0000130c //USB2_HOST1 Bus Gating Reset Register
  #define USB2_HOST1_BGR_REG_USB2_EHCI1_RST_OFFSET 20
  #define USB2_HOST1_BGR_REG_USB2_EHCI1_RST_CLEAR_MASK (0x00100000)
    #define USB2_HOST1_BGR_REG_USB2_EHCI1_RST_ASSERT (0b0)
    #define USB2_HOST1_BGR_REG_USB2_EHCI1_RST_DE_ASSERT (0b1)
  #define USB2_HOST1_BGR_REG_USB2_OHCI1_RST_OFFSET 16
  #define USB2_HOST1_BGR_REG_USB2_OHCI1_RST_CLEAR_MASK (0x00010000)
    #define USB2_HOST1_BGR_REG_USB2_OHCI1_RST_ASSERT (0b0)
    #define USB2_HOST1_BGR_REG_USB2_OHCI1_RST_DE_ASSERT (0b1)
  #define USB2_HOST1_BGR_REG_USB2_EHCI1_GATING_OFFSET 4
  #define USB2_HOST1_BGR_REG_USB2_EHCI1_GATING_CLEAR_MASK (0x00000010)
    #define USB2_HOST1_BGR_REG_USB2_EHCI1_GATING_MASK (0x0)
    #define USB2_HOST1_BGR_REG_USB2_EHCI1_GATING_PASS (0b1)
  #define USB2_HOST1_BGR_REG_USB2_OHCI1_GATING_OFFSET 0
  #define USB2_HOST1_BGR_REG_USB2_OHCI1_GATING_CLEAR_MASK (0x00000001)
    #define USB2_HOST1_BGR_REG_USB2_OHCI1_GATING_MASK (0x0)
    #define USB2_HOST1_BGR_REG_USB2_OHCI1_GATING_PASS (0b1)

#define USB2_HOST2_CLK_REG 0x00001310 //USB2_HOST2 Clock Register
  #define USB2_HOST2_CLK_REG_USB2_HOST2_CLKEN_OFFSET 31
  #define USB2_HOST2_CLK_REG_USB2_HOST2_CLKEN_CLEAR_MASK (0x80000000)
    #define USB2_HOST2_CLK_REG_USB2_HOST2_CLKEN_CLOCK_IS_OFF (0b0)
    #define USB2_HOST2_CLK_REG_USB2_HOST2_CLKEN_CLOCK_IS_ON (0b1)
  #define USB2_HOST2_CLK_REG_USB2_PHY2_RSTN_OFFSET 30
  #define USB2_HOST2_CLK_REG_USB2_PHY2_RSTN_CLEAR_MASK (0x40000000)
    #define USB2_HOST2_CLK_REG_USB2_PHY2_RSTN_ASSERT (0b0)
    #define USB2_HOST2_CLK_REG_USB2_PHY2_RSTN_DE_ASSERT (0b1)
  #define USB2_HOST2_CLK_REG_USB2_HOST2_CLK12M_SEL_OFFSET 24
  #define USB2_HOST2_CLK_REG_USB2_HOST2_CLK12M_SEL_CLEAR_MASK (0x03000000)
    #define USB2_HOST2_CLK_REG_USB2_HOST2_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ (0b000)
    #define USB2_HOST2_CLK_REG_USB2_HOST2_CLK12M_SEL_12M_DIVIDED_FROM_SYS_CLK24M (0b001)
    #define USB2_HOST2_CLK_REG_USB2_HOST2_CLK12M_SEL_CLK32K (0b010)
    #define USB2_HOST2_CLK_REG_USB2_HOST2_CLK12M_SEL_CLK16M_RC (0b011)

#define USB2_HOST2_BGR_REG 0x00001314 //USB2_HOST2 Bus Gating Reset Register
  #define USB2_HOST2_BGR_REG_USB2_EHCI2_RST_OFFSET 20
  #define USB2_HOST2_BGR_REG_USB2_EHCI2_RST_CLEAR_MASK (0x00100000)
    #define USB2_HOST2_BGR_REG_USB2_EHCI2_RST_ASSERT (0b0)
    #define USB2_HOST2_BGR_REG_USB2_EHCI2_RST_DE_ASSERT (0b1)
  #define USB2_HOST2_BGR_REG_USB2_OHCI2_RST_OFFSET 16
  #define USB2_HOST2_BGR_REG_USB2_OHCI2_RST_CLEAR_MASK (0x00010000)
    #define USB2_HOST2_BGR_REG_USB2_OHCI2_RST_ASSERT (0b0)
    #define USB2_HOST2_BGR_REG_USB2_OHCI2_RST_DE_ASSERT (0b1)
  #define USB2_HOST2_BGR_REG_USB2_EHCI2_GATING_OFFSET 4
  #define USB2_HOST2_BGR_REG_USB2_EHCI2_GATING_CLEAR_MASK (0x00000010)
    #define USB2_HOST2_BGR_REG_USB2_EHCI2_GATING_MASK (0x0)
    #define USB2_HOST2_BGR_REG_USB2_EHCI2_GATING_PASS (0b1)
  #define USB2_HOST2_BGR_REG_USB2_OHCI2_GATING_OFFSET 0
  #define USB2_HOST2_BGR_REG_USB2_OHCI2_GATING_CLEAR_MASK (0x00000001)
    #define USB2_HOST2_BGR_REG_USB2_OHCI2_GATING_MASK (0x0)
    #define USB2_HOST2_BGR_REG_USB2_OHCI2_GATING_PASS (0b1)

#define USB2_REF_CLK_REG 0x00001340 //USB2_REF Clock Register
  #define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_OFFSET 31
  #define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLEAR_MASK (0x80000000)
    #define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_ON (0b1)
  #define USB2_REF_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define USB2_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define USB2_REF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define USB2_REF_CLK_REG_CLK_SRC_SEL_HOSC (0b001)

#define USB3_USB2_REF_CLK_REG 0x00001348 //USB3_USB2_REF Clock Register
  #define USB3_USB2_REF_CLK_REG_USB3_USB2_REF_CLK_GATING_OFFSET 31
  #define USB3_USB2_REF_CLK_REG_USB3_USB2_REF_CLK_GATING_CLEAR_MASK (0x80000000)
    #define USB3_USB2_REF_CLK_REG_USB3_USB2_REF_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define USB3_USB2_REF_CLK_REG_USB3_USB2_REF_CLK_GATING_CLOCK_IS_ON (0b1)
  #define USB3_USB2_REF_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define USB3_USB2_REF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define USB3_USB2_REF_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define USB3_USB2_REF_CLK_REG_CLK_SRC_SEL_PERI0_300M (0b001)
    #define USB3_USB2_REF_CLK_REG_CLK_SRC_SEL_HOSC (0b010)
  #define USB3_USB2_REF_CLK_REG_FACTOR_M_OFFSET 0
  #define USB3_USB2_REF_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define USB3_SUSPEND_CLK_REG 0x00001350 //USB3_SUSPEND Clock Register
  #define USB3_SUSPEND_CLK_REG_USB3_SUSPEND_CLK_GATING_OFFSET 31
  #define USB3_SUSPEND_CLK_REG_USB3_SUSPEND_CLK_GATING_CLEAR_MASK (0x80000000)
    #define USB3_SUSPEND_CLK_REG_USB3_SUSPEND_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define USB3_SUSPEND_CLK_REG_USB3_SUSPEND_CLK_GATING_CLOCK_IS_ON (0b1)
  #define USB3_SUSPEND_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define USB3_SUSPEND_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x01000000)
    #define USB3_SUSPEND_CLK_REG_CLK_SRC_SEL_CLK32K (0b0)
    #define USB3_SUSPEND_CLK_REG_CLK_SRC_SEL_HOSC (0b1)
  #define USB3_SUSPEND_CLK_REG_FACTOR_M_OFFSET 0
  #define USB3_SUSPEND_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define USB3_BGR_REG 0x00001354 //USB3 Bus Gating Reset Register
  #define USB3_BGR_REG_USB3_RST_OFFSET 16
  #define USB3_BGR_REG_USB3_RST_CLEAR_MASK (0x00010000)
    #define USB3_BGR_REG_USB3_RST_ASSERT (0b0)
    #define USB3_BGR_REG_USB3_RST_DE_ASSERT (0b1)

#define PCIE0_AUX_CLK_REG 0x00001380 //PCIE0_AUX Clock Register
  #define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_OFFSET 31
  #define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLEAR_MASK (0x80000000)
    #define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define PCIE0_AUX_CLK_REG_PCIE0_AUX_CLK_GATING_CLOCK_IS_ON (0b1)
  #define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x01000000)
    #define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_HOSC (0b0)
    #define PCIE0_AUX_CLK_REG_CLK_SRC_SEL_CLK32K (0b1)
  #define PCIE0_AUX_CLK_REG_FACTOR_M_OFFSET 0
  #define PCIE0_AUX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define PCIE0_BGR_REG 0x0000138c //PCIE0 Bus Gating Reset Register
  #define PCIE0_BGR_REG_PCIE0_RST_OFFSET 17
  #define PCIE0_BGR_REG_PCIE0_RST_CLEAR_MASK (0x00020000)
    #define PCIE0_BGR_REG_PCIE0_RST_ASSERT (0b0)
    #define PCIE0_BGR_REG_PCIE0_RST_DE_ASSERT (0b1)
  #define PCIE0_BGR_REG_PCIE0_PWRUP_RST_OFFSET 16
  #define PCIE0_BGR_REG_PCIE0_PWRUP_RST_CLEAR_MASK (0x00010000)
    #define PCIE0_BGR_REG_PCIE0_PWRUP_RST_ASSERT (0b0)
    #define PCIE0_BGR_REG_PCIE0_PWRUP_RST_DE_ASSERT (0b1)

#define PCIE1_AUX_CLK_REG 0x00001390 //PCIE1_AUX Clock Register
  #define PCIE1_AUX_CLK_REG_PCIE1_AUX_CLK_GATING_OFFSET 31
  #define PCIE1_AUX_CLK_REG_PCIE1_AUX_CLK_GATING_CLEAR_MASK (0x80000000)
    #define PCIE1_AUX_CLK_REG_PCIE1_AUX_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define PCIE1_AUX_CLK_REG_PCIE1_AUX_CLK_GATING_CLOCK_IS_ON (0b1)
  #define PCIE1_AUX_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define PCIE1_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x01000000)
    #define PCIE1_AUX_CLK_REG_CLK_SRC_SEL_HOSC (0b0)
    #define PCIE1_AUX_CLK_REG_CLK_SRC_SEL_CLK32K (0b1)
  #define PCIE1_AUX_CLK_REG_FACTOR_M_OFFSET 0
  #define PCIE1_AUX_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define PCIE1_BGR_REG 0x0000139c //PCIE1 Bus Gating Reset Register
  #define PCIE1_BGR_REG_PCIE1_RST_OFFSET 17
  #define PCIE1_BGR_REG_PCIE1_RST_CLEAR_MASK (0x00020000)
    #define PCIE1_BGR_REG_PCIE1_RST_ASSERT (0b0)
    #define PCIE1_BGR_REG_PCIE1_RST_DE_ASSERT (0b1)
  #define PCIE1_BGR_REG_PCIE1_PWRUP_RST_OFFSET 16
  #define PCIE1_BGR_REG_PCIE1_PWRUP_RST_CLEAR_MASK (0x00010000)
    #define PCIE1_BGR_REG_PCIE1_PWRUP_RST_ASSERT (0b0)
    #define PCIE1_BGR_REG_PCIE1_PWRUP_RST_DE_ASSERT (0b1)

#define SERDES_BGR_REG 0x000013c4 //SERDES Bus Gating Reset Register
  #define SERDES_BGR_REG_SERDES_RST_OFFSET 16
  #define SERDES_BGR_REG_SERDES_RST_CLEAR_MASK (0x00010000)
    #define SERDES_BGR_REG_SERDES_RST_ASSERT (0b0)
    #define SERDES_BGR_REG_SERDES_RST_DE_ASSERT (0b1)

#define GMAC_PTP_CLK_REG 0x00001400 //GMAC_PTP Clock Register
  #define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_OFFSET 31
  #define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLEAR_MASK (0x80000000)
    #define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define GMAC_PTP_CLK_REG_GMAC_PTP_CLK_GATING_CLOCK_IS_ON (0b1)
  #define GMAC_PTP_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define GMAC_PTP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define GMAC_PTP_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define GMAC_PTP_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b001)
    #define GMAC_PTP_CLK_REG_CLK_SRC_SEL_HOSC (0b010)
  #define GMAC_PTP_CLK_REG_FACTOR_M_OFFSET 0
  #define GMAC_PTP_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define GMAC0_PHY_CLK_REG 0x00001410 //GMAC0_PHY Clock Register
  #define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_OFFSET 31
  #define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLEAR_MASK (0x80000000)
    #define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define GMAC0_PHY_CLK_REG_GMAC0_PHY_CLK_GATING_CLOCK_IS_ON (0b1)
  #define GMAC0_PHY_CLK_REG_FACTOR_M_OFFSET 0
  #define GMAC0_PHY_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define GMAC0_BGR_REG 0x0000141c //GMAC0 Bus Gating Reset Register
  #define GMAC0_BGR_REG_GMAC0_AXI_RST_OFFSET 17
  #define GMAC0_BGR_REG_GMAC0_AXI_RST_CLEAR_MASK (0x00020000)
    #define GMAC0_BGR_REG_GMAC0_AXI_RST_ASSERT (0b0)
    #define GMAC0_BGR_REG_GMAC0_AXI_RST_DE_ASSERT (0b1)
  #define GMAC0_BGR_REG_GMAC0_RST_OFFSET 16
  #define GMAC0_BGR_REG_GMAC0_RST_CLEAR_MASK (0x00010000)
    #define GMAC0_BGR_REG_GMAC0_RST_ASSERT (0b0)
    #define GMAC0_BGR_REG_GMAC0_RST_DE_ASSERT (0b1)
  #define GMAC0_BGR_REG_GMAC0_GATING_OFFSET 0
  #define GMAC0_BGR_REG_GMAC0_GATING_CLEAR_MASK (0x00000001)
    #define GMAC0_BGR_REG_GMAC0_GATING_MASK (0x0)
    #define GMAC0_BGR_REG_GMAC0_GATING_PASS (0b1)

#define GMAC1_PHY_CLK_REG 0x00001420 //GMAC1_PHY Clock Register
  #define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_OFFSET 31
  #define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLEAR_MASK (0x80000000)
    #define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define GMAC1_PHY_CLK_REG_GMAC1_PHY_CLK_GATING_CLOCK_IS_ON (0b1)
  #define GMAC1_PHY_CLK_REG_FACTOR_M_OFFSET 0
  #define GMAC1_PHY_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define GMAC1_BGR_REG 0x0000142c //GMAC1 Bus Gating Reset Register
  #define GMAC1_BGR_REG_GMAC1_AXI_RST_OFFSET 17
  #define GMAC1_BGR_REG_GMAC1_AXI_RST_CLEAR_MASK (0x00020000)
    #define GMAC1_BGR_REG_GMAC1_AXI_RST_ASSERT (0b0)
    #define GMAC1_BGR_REG_GMAC1_AXI_RST_DE_ASSERT (0b1)
  #define GMAC1_BGR_REG_GMAC1_RST_OFFSET 16
  #define GMAC1_BGR_REG_GMAC1_RST_CLEAR_MASK (0x00010000)
    #define GMAC1_BGR_REG_GMAC1_RST_ASSERT (0b0)
    #define GMAC1_BGR_REG_GMAC1_RST_DE_ASSERT (0b1)
  #define GMAC1_BGR_REG_GMAC1_GATING_OFFSET 0
  #define GMAC1_BGR_REG_GMAC1_GATING_CLEAR_MASK (0x00000001)
    #define GMAC1_BGR_REG_GMAC1_GATING_MASK (0x0)
    #define GMAC1_BGR_REG_GMAC1_GATING_PASS (0b1)

#define VO0_TCONLCD0_CLK_REG 0x00001500 //VO0_TCONLCD0 Clock Register
  #define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET 31
  #define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON (0b1)
  #define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b000)
    #define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b001)
    #define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b010)
    #define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b011)
    #define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X (0b100)
  #define VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET 0
  #define VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define VO0_TCONLCD0_BGR_REG 0x00001504 //VO0_TCONLCD0 Bus Gating Reset Register
  #define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_OFFSET 16
  #define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK (0x00010000)
    #define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_ASSERT (0b0)
    #define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT (0b1)
  #define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_OFFSET 0
  #define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK (0x00000001)
    #define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_MASK (0x0)
    #define VO0_TCONLCD0_BGR_REG_VO0_TCONLCD0_GATING_PASS (0b1)

#define VO0_TCONLCD1_CLK_REG 0x00001508 //VO0_TCONLCD1 Clock Register
  #define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_OFFSET 31
  #define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLEAR_MASK (0x80000000)
    #define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_ON (0b1)
  #define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b000)
    #define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b001)
    #define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b010)
    #define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b011)
    #define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X (0b100)
  #define VO0_TCONLCD1_CLK_REG_FACTOR_M_OFFSET 0
  #define VO0_TCONLCD1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define VO0_TCONLCD1_BGR_REG 0x0000150c //VO0_TCONLCD1 Bus Gating Reset Register
  #define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_OFFSET 16
  #define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_CLEAR_MASK (0x00010000)
    #define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_ASSERT (0b0)
    #define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_RST_DE_ASSERT (0b1)
  #define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_OFFSET 0
  #define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_CLEAR_MASK (0x00000001)
    #define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_MASK (0x0)
    #define VO0_TCONLCD1_BGR_REG_VO0_TCONLCD1_GATING_PASS (0b1)

#define VO0_TCONLCD2_CLK_REG 0x00001510 //VO0_TCONLCD2 Clock Register
  #define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_OFFSET 31
  #define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLEAR_MASK (0x80000000)
    #define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define VO0_TCONLCD2_CLK_REG_VO0_TCONLCD2_CLK_GATING_CLOCK_IS_ON (0b1)
  #define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b000)
    #define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b001)
    #define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b010)
    #define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b011)
    #define VO0_TCONLCD2_CLK_REG_CLK_SRC_SEL_PERI0PLL2X (0b100)
  #define VO0_TCONLCD2_CLK_REG_FACTOR_M_OFFSET 0
  #define VO0_TCONLCD2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define VO0_TCONLCD2_BGR_REG 0x00001514 //VO0_TCONLCD2 Bus Gating Reset Register
  #define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_OFFSET 16
  #define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_CLEAR_MASK (0x00010000)
    #define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_ASSERT (0b0)
    #define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_RST_DE_ASSERT (0b1)
  #define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_OFFSET 0
  #define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_CLEAR_MASK (0x00000001)
    #define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_MASK (0x0)
    #define VO0_TCONLCD2_BGR_REG_VO0_TCONLCD2_GATING_PASS (0b1)

#define VO0_TCONLCD3_CLK_REG 0x00001518 //VO0_TCONLCD3 Clock Register
  #define VO0_TCONLCD3_CLK_REG_VO0_TCONLCD3_CLK_GATING_OFFSET 31
  #define VO0_TCONLCD3_CLK_REG_VO0_TCONLCD3_CLK_GATING_CLEAR_MASK (0x80000000)
    #define VO0_TCONLCD3_CLK_REG_VO0_TCONLCD3_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define VO0_TCONLCD3_CLK_REG_VO0_TCONLCD3_CLK_GATING_CLOCK_IS_ON (0b1)
  #define VO0_TCONLCD3_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define VO0_TCONLCD3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define VO0_TCONLCD3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b000)
    #define VO0_TCONLCD3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b001)
    #define VO0_TCONLCD3_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b010)
    #define VO0_TCONLCD3_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b011)
    #define VO0_TCONLCD3_CLK_REG_CLK_SRC_SEL_PERI0PLL2X (0b100)
  #define VO0_TCONLCD3_CLK_REG_FACTOR_M_OFFSET 0
  #define VO0_TCONLCD3_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define VO0_TCONLCD3_BGR_REG 0x0000151c //VO0_TCONLCD3 Bus Gating Reset Register
  #define VO0_TCONLCD3_BGR_REG_VO0_TCONLCD3_RST_OFFSET 16
  #define VO0_TCONLCD3_BGR_REG_VO0_TCONLCD3_RST_CLEAR_MASK (0x00010000)
    #define VO0_TCONLCD3_BGR_REG_VO0_TCONLCD3_RST_ASSERT (0b0)
    #define VO0_TCONLCD3_BGR_REG_VO0_TCONLCD3_RST_DE_ASSERT (0b1)
  #define VO0_TCONLCD3_BGR_REG_VO0_TCONLCD3_GATING_OFFSET 0
  #define VO0_TCONLCD3_BGR_REG_VO0_TCONLCD3_GATING_CLEAR_MASK (0x00000001)
    #define VO0_TCONLCD3_BGR_REG_VO0_TCONLCD3_GATING_MASK (0x0)
    #define VO0_TCONLCD3_BGR_REG_VO0_TCONLCD3_GATING_PASS (0b1)

#define LVDS0_BGR_REG 0x00001544 //LVDS0 Bus Gating Reset Register
  #define LVDS0_BGR_REG_LVDS0_RST_OFFSET 16
  #define LVDS0_BGR_REG_LVDS0_RST_CLEAR_MASK (0x00010000)
    #define LVDS0_BGR_REG_LVDS0_RST_ASSERT (0b0)
    #define LVDS0_BGR_REG_LVDS0_RST_DE_ASSERT (0b1)

#define LVDS1_BGR_REG 0x0000154c //LVDS1 Bus Gating Reset Register
  #define LVDS1_BGR_REG_LVDS1_RST_OFFSET 16
  #define LVDS1_BGR_REG_LVDS1_RST_CLEAR_MASK (0x00010000)
    #define LVDS1_BGR_REG_LVDS1_RST_ASSERT (0b0)
    #define LVDS1_BGR_REG_LVDS1_RST_DE_ASSERT (0b1)

#define LVDS2_BGR_REG 0x00001554 //LVDS2 Bus Gating Reset Register
  #define LVDS2_BGR_REG_LVDS2_RST_OFFSET 16
  #define LVDS2_BGR_REG_LVDS2_RST_CLEAR_MASK (0x00010000)
    #define LVDS2_BGR_REG_LVDS2_RST_ASSERT (0b0)
    #define LVDS2_BGR_REG_LVDS2_RST_DE_ASSERT (0b1)

#define DSI0_CLK_REG 0x00001580 //DSI0 Clock register
  #define DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET 31
  #define DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON (0b1)
  #define DSI0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define DSI0_CLK_REG_CLK_SRC_SEL_HOSC (0b000)
    #define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b001)
    #define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M (0b010)
  #define DSI0_CLK_REG_FACTOR_M_OFFSET 0
  #define DSI0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define DSI0_BGR_REG 0x00001584 //DSI0 Bus Gating Reset Register
  #define DSI0_BGR_REG_DSI0_RST_OFFSET 16
  #define DSI0_BGR_REG_DSI0_RST_CLEAR_MASK (0x00010000)
    #define DSI0_BGR_REG_DSI0_RST_ASSERT (0b0)
    #define DSI0_BGR_REG_DSI0_RST_DE_ASSERT (0b1)
  #define DSI0_BGR_REG_DSI0_GATING_OFFSET 0
  #define DSI0_BGR_REG_DSI0_GATING_CLEAR_MASK (0x00000001)
    #define DSI0_BGR_REG_DSI0_GATING_MASK (0x0)
    #define DSI0_BGR_REG_DSI0_GATING_PASS (0b1)

#define DSI1_CLK_REG 0x00001588 //DSI1 Clock Register
  #define DSI1_CLK_REG_DSI1_CLK_GATING_OFFSET 31
  #define DSI1_CLK_REG_DSI1_CLK_GATING_CLEAR_MASK (0x80000000)
    #define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_ON (0b1)
  #define DSI1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define DSI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define DSI1_CLK_REG_CLK_SRC_SEL_HOSC (0b000)
    #define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_200M (0b001)
    #define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_150M (0b010)
  #define DSI1_CLK_REG_FACTOR_M_OFFSET 0
  #define DSI1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define DSI1_BGR_REG 0x0000158c //DSI1 Bus Gating Reset Register
  #define DSI1_BGR_REG_DSI1_RST_OFFSET 16
  #define DSI1_BGR_REG_DSI1_RST_CLEAR_MASK (0x00010000)
    #define DSI1_BGR_REG_DSI1_RST_ASSERT (0b0)
    #define DSI1_BGR_REG_DSI1_RST_DE_ASSERT (0b1)
  #define DSI1_BGR_REG_DSI1_GATING_OFFSET 0
  #define DSI1_BGR_REG_DSI1_GATING_CLEAR_MASK (0x00000001)
    #define DSI1_BGR_REG_DSI1_GATING_MASK (0x0)
    #define DSI1_BGR_REG_DSI1_GATING_PASS (0b1)

#define COMBPHY0_CLK_REG 0x000015c0 //COMBPHY0 Clock Register
  #define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_OFFSET 31
  #define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_ON (0b1)
  #define COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b000)
    #define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b001)
    #define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b010)
    #define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b011)
    #define COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X (0b100)
  #define COMBPHY0_CLK_REG_FACTOR_M_OFFSET 0
  #define COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define COMBPHY1_CLK_REG 0x000015c4 //COMBPHY1 Clock Register
  #define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_OFFSET 31
  #define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLEAR_MASK (0x80000000)
    #define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_ON (0b1)
  #define COMBPHY1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define COMBPHY1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b000)
    #define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b001)
    #define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b010)
    #define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b011)
    #define COMBPHY1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X (0b100)
  #define COMBPHY1_CLK_REG_FACTOR_M_OFFSET 0
  #define COMBPHY1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define TCONTV0_CLK_REG 0x00001600 //TCONTV0 Clock Register
  #define TCONTV0_CLK_REG_TCONTV0_CLK_GATING_OFFSET 31
  #define TCONTV0_CLK_REG_TCONTV0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define TCONTV0_CLK_REG_TCONTV0_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define TCONTV0_CLK_REG_TCONTV0_CLK_GATING_CLOCK_IS_ON (0b1)
  #define TCONTV0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TCONTV0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define TCONTV0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b000)
    #define TCONTV0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b001)
    #define TCONTV0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b010)
    #define TCONTV0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b011)
    #define TCONTV0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X (0b100)
  #define TCONTV0_CLK_REG_FACTOR_N_OFFSET 8
  #define TCONTV0_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define TCONTV0_CLK_REG_FACTOR_M_OFFSET 0
  #define TCONTV0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define TCONTV0_BGR_REG 0x00001604 //TCONTV0 Bus Gating Reset Register
  #define TCONTV0_BGR_REG_TCONTV0_RST_OFFSET 16
  #define TCONTV0_BGR_REG_TCONTV0_RST_CLEAR_MASK (0x00010000)
    #define TCONTV0_BGR_REG_TCONTV0_RST_ASSERT (0b0)
    #define TCONTV0_BGR_REG_TCONTV0_RST_DE_ASSERT (0b1)
  #define TCONTV0_BGR_REG_TCONTV0_GATING_OFFSET 0
  #define TCONTV0_BGR_REG_TCONTV0_GATING_CLEAR_MASK (0x00000001)
    #define TCONTV0_BGR_REG_TCONTV0_GATING_MASK (0x0)
    #define TCONTV0_BGR_REG_TCONTV0_GATING_PASS (0b1)

#define TCONTV1_BGR_REG 0x0000160c //TCONTV1 Bus Gating Reset Register
  #define TCONTV1_BGR_REG_TCONTV1_RST_OFFSET 16
  #define TCONTV1_BGR_REG_TCONTV1_RST_CLEAR_MASK (0x00010000)
    #define TCONTV1_BGR_REG_TCONTV1_RST_ASSERT (0b0)
    #define TCONTV1_BGR_REG_TCONTV1_RST_DE_ASSERT (0b1)
  #define TCONTV1_BGR_REG_TCONTV1_GATING_OFFSET 0
  #define TCONTV1_BGR_REG_TCONTV1_GATING_CLEAR_MASK (0x00000001)
    #define TCONTV1_BGR_REG_TCONTV1_GATING_MASK (0x0)
    #define TCONTV1_BGR_REG_TCONTV1_GATING_PASS (0b1)

#define TCONTV2_BGR_REG 0x00001614 //TCONTV2 Bus Gating Reset Register
  #define TCONTV2_BGR_REG_TCONTV2_RST_OFFSET 16
  #define TCONTV2_BGR_REG_TCONTV2_RST_CLEAR_MASK (0x00010000)
    #define TCONTV2_BGR_REG_TCONTV2_RST_ASSERT (0b0)
    #define TCONTV2_BGR_REG_TCONTV2_RST_DE_ASSERT (0b1)
  #define TCONTV2_BGR_REG_TCONTV2_GATING_OFFSET 0
  #define TCONTV2_BGR_REG_TCONTV2_GATING_CLEAR_MASK (0x00000001)
    #define TCONTV2_BGR_REG_TCONTV2_GATING_MASK (0x0)
    #define TCONTV2_BGR_REG_TCONTV2_GATING_PASS (0b1)

#define EDP_CLK0_CLK_REG 0x00001640 //EDP_CLK0 Clock Register
  #define EDP_CLK0_CLK_REG_EDP_CLK0_CLK_GATING_OFFSET 31
  #define EDP_CLK0_CLK_REG_EDP_CLK0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define EDP_CLK0_CLK_REG_EDP_CLK0_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define EDP_CLK0_CLK_REG_EDP_CLK0_CLK_GATING_CLOCK_IS_ON (0b1)
  #define EDP_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define EDP_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define EDP_CLK0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b000)
    #define EDP_CLK0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b001)
    #define EDP_CLK0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b010)
    #define EDP_CLK0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b011)
    #define EDP_CLK0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X (0b100)
  #define EDP_CLK0_CLK_REG_FACTOR_M_OFFSET 0
  #define EDP_CLK0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define EDP_CLK1_CLK_REG 0x00001644 //EDP_CLK1 Clock Register
  #define EDP_CLK1_CLK_REG_EDP_CLK1_CLK_GATING_OFFSET 31
  #define EDP_CLK1_CLK_REG_EDP_CLK1_CLK_GATING_CLEAR_MASK (0x80000000)
    #define EDP_CLK1_CLK_REG_EDP_CLK1_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define EDP_CLK1_CLK_REG_EDP_CLK1_CLK_GATING_CLOCK_IS_ON (0b1)
  #define EDP_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define EDP_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define EDP_CLK1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b000)
    #define EDP_CLK1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b001)
    #define EDP_CLK1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b010)
    #define EDP_CLK1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b011)
    #define EDP_CLK1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X (0b100)
  #define EDP_CLK1_CLK_REG_FACTOR_M_OFFSET 0
  #define EDP_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define EDP_BGR_REG 0x0000164c //EDP Bus Gating Reset Register
  #define EDP_BGR_REG_EDP_RST_OFFSET 16
  #define EDP_BGR_REG_EDP_RST_CLEAR_MASK (0x00010000)
    #define EDP_BGR_REG_EDP_RST_ASSERT (0b0)
    #define EDP_BGR_REG_EDP_RST_DE_ASSERT (0b1)
  #define EDP_BGR_REG_EDP_GATING_OFFSET 0
  #define EDP_BGR_REG_EDP_GATING_CLEAR_MASK (0x00000001)
    #define EDP_BGR_REG_EDP_GATING_MASK (0x0)
    #define EDP_BGR_REG_EDP_GATING_PASS (0b1)

#define HDMI_REF_CLK_REG 0x00001680 //HDMI REF Clock Register
  #define HDMI_REF_CLK_REG_HDMI_REF_CLK_GATING_OFFSET 31
  #define HDMI_REF_CLK_REG_HDMI_REF_CLK_GATING_CLEAR_MASK (0x80000000)
    #define HDMI_REF_CLK_REG_HDMI_REF_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define HDMI_REF_CLK_REG_HDMI_REF_CLK_GATING_CLOCK_IS_ON (0b1)

#define HDMI_PRE_CLK_REG 0x00001684 //HDMI PRE Clock Register
  #define HDMI_PRE_CLK_REG_HDMI_PRE_CLK_GATING_OFFSET 31
  #define HDMI_PRE_CLK_REG_HDMI_PRE_CLK_GATING_CLEAR_MASK (0x80000000)
    #define HDMI_PRE_CLK_REG_HDMI_PRE_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define HDMI_PRE_CLK_REG_HDMI_PRE_CLK_GATING_CLOCK_IS_ON (0b1)
  #define HDMI_PRE_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define HDMI_PRE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define HDMI_PRE_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b000)
    #define HDMI_PRE_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b001)
    #define HDMI_PRE_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b010)
    #define HDMI_PRE_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b011)
    #define HDMI_PRE_CLK_REG_CLK_SRC_SEL_PERI0PLL2X (0b100)
  #define HDMI_PRE_CLK_REG_FACTOR_N_OFFSET 8
  #define HDMI_PRE_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define HDMI_PRE_CLK_REG_FACTOR_M_OFFSET 0
  #define HDMI_PRE_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define HDMI_BGR_REG 0x0000168c //HDMI Bus Gating Reset Register
  #define HDMI_BGR_REG_HDMI_HDCP_RST_OFFSET 18
  #define HDMI_BGR_REG_HDMI_HDCP_RST_CLEAR_MASK (0x00040000)
    #define HDMI_BGR_REG_HDMI_HDCP_RST_ASSERT (0b0)
    #define HDMI_BGR_REG_HDMI_HDCP_RST_DE_ASSERT (0b1)
  #define HDMI_BGR_REG_HDMI_SUB_RST_OFFSET 17
  #define HDMI_BGR_REG_HDMI_SUB_RST_CLEAR_MASK (0x00020000)
    #define HDMI_BGR_REG_HDMI_SUB_RST_ASSERT (0b0)
    #define HDMI_BGR_REG_HDMI_SUB_RST_DE_ASSERT (0b1)
  #define HDMI_BGR_REG_HDMI_MAIN_RST_OFFSET 16
  #define HDMI_BGR_REG_HDMI_MAIN_RST_CLEAR_MASK (0x00010000)
    #define HDMI_BGR_REG_HDMI_MAIN_RST_ASSERT (0b0)
    #define HDMI_BGR_REG_HDMI_MAIN_RST_DE_ASSERT (0b1)
  #define HDMI_BGR_REG_HDMI_HDCP_GATING_OFFSET 1
  #define HDMI_BGR_REG_HDMI_HDCP_GATING_CLEAR_MASK (0x00000002)
    #define HDMI_BGR_REG_HDMI_HDCP_GATING_MASK (0x0)
    #define HDMI_BGR_REG_HDMI_HDCP_GATING_PASS (0b1)
  #define HDMI_BGR_REG_HDMI_GATING_OFFSET 0
  #define HDMI_BGR_REG_HDMI_GATING_CLEAR_MASK (0x00000001)
    #define HDMI_BGR_REG_HDMI_GATING_MASK (0x0)
    #define HDMI_BGR_REG_HDMI_GATING_PASS (0b1)

#define DPSS_TOP0_BGR_REG 0x000016c4 //DPSS_TOP0 Bus Gating Reset Register
  #define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_OFFSET 16
  #define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_CLEAR_MASK (0x00010000)
    #define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_ASSERT (0b0)
    #define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_DE_ASSERT (0b1)
  #define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_OFFSET 0
  #define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_CLEAR_MASK (0x00000001)
    #define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_MASK (0x0)
    #define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_PASS (0b1)

#define DPSS_TOP1_BGR_REG 0x000016cc //DPSS_TOP1 Bus Gating Reset Register
  #define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_OFFSET 16
  #define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_CLEAR_MASK (0x00010000)
    #define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_ASSERT (0b0)
    #define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_DE_ASSERT (0b1)
  #define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_OFFSET 0
  #define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_CLEAR_MASK (0x00000001)
    #define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_MASK (0x0)
    #define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_PASS (0b1)

#define VIDEO_OUT0_BGR_REG 0x000016e4 //VIDEO_OUT0 Bus Gating Reset Register
  #define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_OFFSET 16
  #define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_CLEAR_MASK (0x00010000)
    #define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_ASSERT (0b0)
    #define VIDEO_OUT0_BGR_REG_VIDEO_OUT0_RST_DE_ASSERT (0b1)

#define VIDEO_OUT1_BGR_REG 0x000016ec //VIDEO_OUT1 Bus Gating Reset Register
  #define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_OFFSET 16
  #define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_CLEAR_MASK (0x00010000)
    #define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_ASSERT (0b0)
    #define VIDEO_OUT1_BGR_REG_VIDEO_OUT1_RST_DE_ASSERT (0b1)

#define LEDC_CLK_REG 0x00001700 //LEDC Clock Register
  #define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET 31
  #define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK (0x80000000)
    #define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON (0b1)
  #define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define LEDC_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M (0b001)
    #define LEDC_CLK_REG_CLK_SRC_SEL_HOSC (0b010)
  #define LEDC_CLK_REG_FACTOR_M_OFFSET 0
  #define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define LEDC_BGR_REG 0x00001704 //LEDC Bus Gating Reset register
  #define LEDC_BGR_REG_LEDC_RST_OFFSET 16
  #define LEDC_BGR_REG_LEDC_RST_CLEAR_MASK (0x00010000)
    #define LEDC_BGR_REG_LEDC_RST_ASSERT (0b0)
    #define LEDC_BGR_REG_LEDC_RST_DE_ASSERT (0b1)
  #define LEDC_BGR_REG_LEDC_GATING_OFFSET 0
  #define LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK (0x00000001)
    #define LEDC_BGR_REG_LEDC_GATING_MASK (0x0)
    #define LEDC_BGR_REG_LEDC_GATING_PASS (0b1)

#define CSI_MASTER0_CLK_REG 0x00001800 //CSI Master0 Clock Register
  #define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET 31
  #define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK (0x80000000)
    #define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON (0b1)
  #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b001)
    #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X (0b010)
    #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b011)
    #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X (0b100)
    #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b101)
    #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X (0b110)
    #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_HOSC (0b111)
  #define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET 8
  #define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET 0
  #define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define CSI_MASTER1_CLK_REG 0x00001804 //CSI Master1 Clock Register
  #define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET 31
  #define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK (0x80000000)
    #define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON (0b1)
  #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b001)
    #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X (0b010)
    #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b011)
    #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X (0b100)
    #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b101)
    #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X (0b110)
    #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_HOSC (0b111)
  #define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET 8
  #define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET 0
  #define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define CSI_MASTER2_CLK_REG 0x00001808 //CSI Master2 Clock Register
  #define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET 31
  #define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK (0x80000000)
    #define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON (0b1)
  #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b001)
    #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X (0b010)
    #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b011)
    #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X (0b100)
    #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b101)
    #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X (0b110)
    #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_HOSC (0b111)
  #define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET 8
  #define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET 0
  #define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define CSI_MASTER3_CLK_REG 0x0000180c //CSI Master3 Clock Register
  #define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_OFFSET 31
  #define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLEAR_MASK (0x80000000)
    #define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_ON (0b1)
  #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_SYS_CLK24M (0b000)
    #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b001)
    #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL3X (0b010)
    #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b011)
    #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL3X (0b100)
    #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b101)
    #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO2PLL3X (0b110)
    #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_HOSC (0b111)
  #define CSI_MASTER3_CLK_REG_FACTOR_N_OFFSET 8
  #define CSI_MASTER3_CLK_REG_FACTOR_N_CLEAR_MASK (0x00001f00)
  #define CSI_MASTER3_CLK_REG_FACTOR_M_OFFSET 0
  #define CSI_MASTER3_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define CSI_CLK_REG 0x00001840 //CSI Clock Register
  #define CSI_CLK_REG_CSI_CLK_GATING_OFFSET 31
  #define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK (0x80000000)
    #define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON (0b1)
  #define CSI_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define CSI_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b000)
    #define CSI_CLK_REG_CLK_SRC_SEL_DEPLL4X (0b001)
    #define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M (0b010)
    #define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M (0b011)
    #define CSI_CLK_REG_CLK_SRC_SEL_PERI0_600M (0b100)
    #define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b101)
    #define CSI_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b110)
    #define CSI_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b111)
  #define CSI_CLK_REG_FACTOR_M_OFFSET 0
  #define CSI_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define CSI_BGR_REG 0x00001844 //CSI Bus Gating Reset Register
  #define CSI_BGR_REG_CSI_RST_OFFSET 16
  #define CSI_BGR_REG_CSI_RST_CLEAR_MASK (0x00010000)
    #define CSI_BGR_REG_CSI_RST_ASSERT (0b0)
    #define CSI_BGR_REG_CSI_RST_DE_ASSERT (0b1)
  #define CSI_BGR_REG_CSI_GATING_OFFSET 0
  #define CSI_BGR_REG_CSI_GATING_CLEAR_MASK (0x00000001)
    #define CSI_BGR_REG_CSI_GATING_MASK (0x0)
    #define CSI_BGR_REG_CSI_GATING_PASS (0b1)

#define ISP_CLK_REG 0x00001860 //ISP Clock Register
  #define ISP_CLK_REG_ISP_CLK_GATING_OFFSET 31
  #define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK (0x80000000)
    #define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF (0b0)
    #define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON (0b1)
  #define ISP_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK (0x07000000)
    #define ISP_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X (0b000)
    #define ISP_CLK_REG_CLK_SRC_SEL_PERI0_480M (0b001)
    #define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M (0b010)
    #define ISP_CLK_REG_CLK_SRC_SEL_PERI0_600M (0b011)
    #define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X (0b100)
    #define ISP_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X (0b101)
    #define ISP_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X (0b110)
  #define ISP_CLK_REG_FACTOR_M_OFFSET 0
  #define ISP_CLK_REG_FACTOR_M_CLEAR_MASK (0x0000001f)

#define VIDEO_IN_BGR_REG 0x00001884 //VIDEO_IN Bus Gating Reset Register
  #define VIDEO_IN_BGR_REG_VIDEO_IN_RST_OFFSET 16
  #define VIDEO_IN_BGR_REG_VIDEO_IN_RST_CLEAR_MASK (0x00010000)
    #define VIDEO_IN_BGR_REG_VIDEO_IN_RST_ASSERT (0b0)
    #define VIDEO_IN_BGR_REG_VIDEO_IN_RST_DE_ASSERT (0b1)

#define DDRPLL_GATE_EN_REG 0x00001904 //DDRPLL Gate Enable Register
  #define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_OFFSET 16
  #define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_CLEAR_MASK (0x00010000)
    #define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_DISABLE (0b0)
    #define DDRPLL_GATE_EN_REG_DDRPLL_GATE_SW_CFG_ENABLE (0b1)
  #define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_OFFSET 0
  #define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_CLEAR_MASK (0x00000001)
    #define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_AUTO (0b0)
    #define DDRPLL_GATE_EN_REG_DDRPLL_AUTO_GATE_EN_NO_AUTO (0b1)

#define PERI0PLL_GATE_EN_REG 0x00001908 //PERI0PLL Gate Enable Register
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_OFFSET 31
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_CLEAR_MASK (0x80000000)
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_DISABLE (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_DSP_GATE_EN_ENABLE (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET 27
  #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK (0x08000000)
    #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET 26
  #define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK (0x04000000)
    #define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET 25
  #define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK (0x02000000)
    #define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET 24
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK (0x01000000)
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET 23
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK (0x00800000)
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET 22
  #define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK (0x00400000)
    #define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET 21
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK (0x00200000)
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET 20
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK (0x00100000)
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET 19
  #define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK (0x00080000)
    #define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET 18
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK (0x00040000)
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET 17
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK (0x00020000)
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET 16
  #define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK (0x00010000)
    #define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET 11
  #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK (0x00000800)
    #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET 10
  #define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK (0x00000400)
    #define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET 9
  #define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK (0x00000200)
    #define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET 8
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000100)
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET 7
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK (0x00000080)
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET 6
  #define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK (0x00000040)
    #define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET 5
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000020)
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET 4
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK (0x00000010)
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET 3
  #define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK (0x00000008)
    #define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET 2
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000004)
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET 1
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK (0x00000002)
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET 0
  #define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK (0x00000001)
    #define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO (0b1)

#define PERI1PLL_GATE_EN_REG 0x0000190c //PERI1PLL Gate Enable Register
  #define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_OFFSET 31
  #define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_CLEAR_MASK (0x80000000)
    #define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_DISABLE (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_300M_DSP_GATE_EN_ENABLE (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_OFFSET 27
  #define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_CLEAR_MASK (0x08000000)
    #define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_800M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_OFFSET 26
  #define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_CLEAR_MASK (0x04000000)
    #define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_DISABLE (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_ALL_CFG_ENABLE (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_OFFSET 25
  #define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_CLEAR_MASK (0x02000000)
    #define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_600M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_OFFSET 24
  #define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_CLEAR_MASK (0x01000000)
    #define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_DISABLE (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_ALL_CFG_ENABLE (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_OFFSET 23
  #define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_CLEAR_MASK (0x00800000)
    #define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_480M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_OFFSET 22
  #define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_CLEAR_MASK (0x00400000)
    #define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_160M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_OFFSET 21
  #define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_CLEAR_MASK (0x00200000)
    #define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_DISABLE (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_ALL_CFG_ENABLE (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_OFFSET 20
  #define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_CLEAR_MASK (0x00100000)
    #define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_300M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_OFFSET 19
  #define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_CLEAR_MASK (0x00080000)
    #define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_150M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_OFFSET 18
  #define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_CLEAR_MASK (0x00040000)
    #define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_DISABLE (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_ALL_CFG_ENABLE (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_OFFSET 17
  #define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_CLEAR_MASK (0x00020000)
    #define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_400M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_OFFSET 16
  #define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_CLEAR_MASK (0x00010000)
    #define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_DISABLE (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_200M_GATE_SW_CFG_ENABLE (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_OFFSET 11
  #define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_CLEAR_MASK (0x00000800)
    #define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_800M_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_OFFSET 10
  #define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000400)
    #define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_AUTO (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_ALL_NO_AUTO (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_OFFSET 9
  #define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_CLEAR_MASK (0x00000200)
    #define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_600M_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_OFFSET 8
  #define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000100)
    #define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_AUTO (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_ALL_NO_AUTO (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_OFFSET 7
  #define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_CLEAR_MASK (0x00000080)
    #define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_480M_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_OFFSET 6
  #define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_CLEAR_MASK (0x00000040)
    #define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_160M_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_OFFSET 5
  #define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000020)
    #define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_AUTO (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_ALL_NO_AUTO (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_OFFSET 4
  #define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_CLEAR_MASK (0x00000010)
    #define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_300M_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_OFFSET 3
  #define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_CLEAR_MASK (0x00000008)
    #define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_150M_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_OFFSET 2
  #define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_CLEAR_MASK (0x00000004)
    #define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_AUTO (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_ALL_NO_AUTO (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_OFFSET 1
  #define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_CLEAR_MASK (0x00000002)
    #define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_400M_AUTO_GATE_EN_NO_AUTO (0b1)
  #define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_OFFSET 0
  #define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_CLEAR_MASK (0x00000001)
    #define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_AUTO (0b0)
    #define PERI1PLL_GATE_EN_REG_PERI1_200M_AUTO_GATE_EN_NO_AUTO (0b1)

#define VIDEOPLL_GATE_EN_REG 0x00001910 //VIDEOPLL Gate Enable Register
  #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL3X_GATE_SW_CFG_OFFSET 23
  #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL3X_GATE_SW_CFG_CLEAR_MASK (0x00800000)
    #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL3X_GATE_SW_CFG_DISABLE (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL3X_GATE_SW_CFG_ENABLE (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_OFFSET 22
  #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_CLEAR_MASK (0x00400000)
    #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_DISABLE (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_GATE_SW_CFG_ENABLE (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_OFFSET 21
  #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_CLEAR_MASK (0x00200000)
    #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_DISABLE (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_GATE_SW_CFG_ENABLE (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_OFFSET 20
  #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_CLEAR_MASK (0x00100000)
    #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_DISABLE (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_GATE_SW_CFG_ENABLE (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL4X_GATE_SW_CFG_OFFSET 19
  #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL4X_GATE_SW_CFG_CLEAR_MASK (0x00080000)
    #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL4X_GATE_SW_CFG_DISABLE (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL4X_GATE_SW_CFG_ENABLE (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_OFFSET 18
  #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_CLEAR_MASK (0x00040000)
    #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_DISABLE (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_GATE_SW_CFG_ENABLE (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_OFFSET 17
  #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_CLEAR_MASK (0x00020000)
    #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_DISABLE (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_GATE_SW_CFG_ENABLE (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_OFFSET 16
  #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_CLEAR_MASK (0x00010000)
    #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_DISABLE (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_GATE_SW_CFG_ENABLE (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL3X_AUTO_GATE_EN_OFFSET 7
  #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL3X_AUTO_GATE_EN_CLEAR_MASK (0x00000080)
    #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL3X_AUTO_GATE_EN_AUTO (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL3X_AUTO_GATE_EN_NO_AUTO (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_OFFSET 6
  #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_CLEAR_MASK (0x00000040)
    #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_AUTO (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL3X_AUTO_GATE_EN_NO_AUTO (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_OFFSET 5
  #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_CLEAR_MASK (0x00000020)
    #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_AUTO (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL3X_AUTO_GATE_EN_NO_AUTO (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_OFFSET 4
  #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_CLEAR_MASK (0x00000010)
    #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_AUTO (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL3X_AUTO_GATE_EN_NO_AUTO (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL4X_AUTO_GATE_EN_OFFSET 3
  #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000008)
    #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL4X_AUTO_GATE_EN_AUTO (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO3PLL4X_AUTO_GATE_EN_NO_AUTO (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_OFFSET 2
  #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000004)
    #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_AUTO (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO2PLL4X_AUTO_GATE_EN_NO_AUTO (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_OFFSET 1
  #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000002)
    #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_AUTO (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO1PLL4X_AUTO_GATE_EN_NO_AUTO (0b1)
  #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_OFFSET 0
  #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000001)
    #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_AUTO (0b0)
    #define VIDEOPLL_GATE_EN_REG_VIDEO0PLL4X_AUTO_GATE_EN_NO_AUTO (0b1)

#define GPUPLL_GATE_EN_REG 0x00001914 //GPUPLL Gate Enable Register
  #define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_OFFSET 16
  #define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_CLEAR_MASK (0x00010000)
    #define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_DISABLE (0b0)
    #define GPUPLL_GATE_EN_REG_GPU0PLL_GATE_SW_CFG_ENABLE (0b1)
  #define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_OFFSET 0
  #define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_CLEAR_MASK (0x00000001)
    #define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_AUTO (0b0)
    #define GPUPLL_GATE_EN_REG_GPU0PLL_AUTO_GATE_EN_NO_AUTO (0b1)

#define VEPLL_GATE_EN_REG 0x00001918 //VEPLL Gate Enable Register
  #define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_OFFSET 17
  #define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_CLEAR_MASK (0x00020000)
    #define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_DISABLE (0b0)
    #define VEPLL_GATE_EN_REG_VE1PLL_GATE_SW_CFG_ENABLE (0b1)
  #define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_OFFSET 16
  #define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_CLEAR_MASK (0x00010000)
    #define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_DISABLE (0b0)
    #define VEPLL_GATE_EN_REG_VE0PLL_GATE_SW_CFG_ENABLE (0b1)
  #define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_OFFSET 1
  #define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_CLEAR_MASK (0x00000002)
    #define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_AUTO (0b0)
    #define VEPLL_GATE_EN_REG_VE1PLL_AUTO_GATE_EN_NO_AUTO (0b1)
  #define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_OFFSET 0
  #define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_CLEAR_MASK (0x00000001)
    #define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_AUTO (0b0)
    #define VEPLL_GATE_EN_REG_VE0PLL_AUTO_GATE_EN_NO_AUTO (0b1)

#define AUDIOPLL_GATE_EN_REG 0x0000191c //AUDIOPLL Gate Enable Register
  #define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_OFFSET 16
  #define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_CLEAR_MASK (0x00010000)
    #define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_DISABLE (0b0)
    #define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_GATE_SW_CFG_ENABLE (0b1)
  #define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_OFFSET 0
  #define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000001)
    #define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_AUTO (0b0)
    #define AUDIOPLL_GATE_EN_REG_AUDIO0PLL4X_AUTO_GATE_EN_NO_AUTO (0b1)

#define NPUPLL_GATE_EN_REG 0x00001920 //NPUPLL Gate Enable Register
  #define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_OFFSET 16
  #define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_CLEAR_MASK (0x00010000)
    #define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_DISABLE (0b0)
    #define NPUPLL_GATE_EN_REG_NPUPLL_GATE_SW_CFG_ENABLE (0b1)
  #define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_OFFSET 0
  #define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_CLEAR_MASK (0x00000001)
    #define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_AUTO (0b0)
    #define NPUPLL_GATE_EN_REG_NPUPLL_AUTO_GATE_EN_NO_AUTO (0b1)

#define DEPLL_GATE_EN_REG 0x00001928 //DEPLL Gate Enable Register
  #define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_OFFSET 17
  #define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_CLEAR_MASK (0x00020000)
    #define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_DISABLE (0b0)
    #define DEPLL_GATE_EN_REG_DEPLL3X_GATE_SW_CFG_ENABLE (0b1)
  #define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_OFFSET 16
  #define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_CLEAR_MASK (0x00010000)
    #define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_DISABLE (0b0)
    #define DEPLL_GATE_EN_REG_DEPLL4X_GATE_SW_CFG_ENABLE (0b1)
  #define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_OFFSET 1
  #define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_CLEAR_MASK (0x00000002)
    #define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_AUTO (0b0)
    #define DEPLL_GATE_EN_REG_DEPLL3X_AUTO_GATE_EN_NO_AUTO (0b1)
  #define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_OFFSET 0
  #define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_CLEAR_MASK (0x00000001)
    #define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_AUTO (0b0)
    #define DEPLL_GATE_EN_REG_DEPLL4X_AUTO_GATE_EN_NO_AUTO (0b1)

#define CCIPLL_GATE_EN_REG 0x00001930 //CCIPLL Gate Enable Register
  #define CCIPLL_GATE_EN_REG_CCIPLL_GATE_SW_CFG_OFFSET 16
  #define CCIPLL_GATE_EN_REG_CCIPLL_GATE_SW_CFG_CLEAR_MASK (0x00010000)
    #define CCIPLL_GATE_EN_REG_CCIPLL_GATE_SW_CFG_DISABLE (0b0)
    #define CCIPLL_GATE_EN_REG_CCIPLL_GATE_SW_CFG_ENABLE (0b1)
  #define CCIPLL_GATE_EN_REG_CCIPLL_AUTO_GATE_EN_OFFSET 0
  #define CCIPLL_GATE_EN_REG_CCIPLL_AUTO_GATE_EN_CLEAR_MASK (0x00000001)
    #define CCIPLL_GATE_EN_REG_CCIPLL_AUTO_GATE_EN_AUTO (0b0)
    #define CCIPLL_GATE_EN_REG_CCIPLL_AUTO_GATE_EN_NO_AUTO (0b1)

#define DDRPLL_GATE_STAT_REG 0x00001984 //DDRPLL Gate Status Register
  #define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_OFFSET 16
  #define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_CLEAR_MASK (0x00010000)
    #define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_DISABLE (0b0)
    #define DDRPLL_GATE_STAT_REG_DDRPLL_GATE_STAT_ENABLE (0b1)

#define PERI0PLL_GATE_STAT_REG 0x00001988 //PERI0PLL Gate Status Register
  #define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_OFFSET 27
  #define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_CLEAR_MASK (0x08000000)
    #define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_DISABLE (0b0)
    #define PERI0PLL_GATE_STAT_REG_PERI0PLL2X_GATE_STAT_ENABLE (0b1)
  #define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_OFFSET 26
  #define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_CLEAR_MASK (0x04000000)
    #define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_DISABLE (0b0)
    #define PERI0PLL_GATE_STAT_REG_PERI0_800M_GATE_STAT_ENABLE (0b1)
  #define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_OFFSET 25
  #define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_CLEAR_MASK (0x02000000)
    #define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_DISABLE (0b0)
    #define PERI0PLL_GATE_STAT_REG_PERI0_600M_GATE_STAT_ENABLE (0b1)
  #define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_OFFSET 24
  #define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_CLEAR_MASK (0x01000000)
    #define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_DISABLE (0b0)
    #define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_ALL_STAT_ENABLE (0b1)
  #define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_OFFSET 23
  #define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_CLEAR_MASK (0x00800000)
    #define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_DISABLE (0b0)
    #define PERI0PLL_GATE_STAT_REG_PERI0_480M_GATE_STAT_ENABLE (0b1)
  #define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_OFFSET 22
  #define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_CLEAR_MASK (0x00400000)
    #define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_DISABLE (0b0)
    #define PERI0PLL_GATE_STAT_REG_PERI0_160M_GATE_STAT_ENABLE (0b1)
  #define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_OFFSET 21
  #define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_CLEAR_MASK (0x00200000)
    #define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_DISABLE (0b0)
    #define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_ALL_STAT_ENABLE (0b1)
  #define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_OFFSET 20
  #define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_CLEAR_MASK (0x00100000)
    #define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_DISABLE (0b0)
    #define PERI0PLL_GATE_STAT_REG_PERI0_300M_GATE_STAT_ENABLE (0b1)
  #define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_OFFSET 19
  #define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_CLEAR_MASK (0x00080000)
    #define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_DISABLE (0b0)
    #define PERI0PLL_GATE_STAT_REG_PERI0_150M_GATE_STAT_ENABLE (0b1)
  #define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_OFFSET 18
  #define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_CLEAR_MASK (0x00040000)
    #define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_DISABLE (0b0)
    #define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_ALL_STAT_ENABLE (0b1)
  #define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_OFFSET 17
  #define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_CLEAR_MASK (0x00020000)
    #define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_DISABLE (0b0)
    #define PERI0PLL_GATE_STAT_REG_PERI0_400M_GATE_STAT_ENABLE (0b1)
  #define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_OFFSET 16
  #define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_CLEAR_MASK (0x00010000)
    #define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_DISABLE (0b0)
    #define PERI0PLL_GATE_STAT_REG_PERI0_200M_GATE_STAT_ENABLE (0b1)

#define PERI1PLL_GATE_STAT_REG 0x0000198c //PERI1PLL Gate Status register
  #define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_OFFSET 27
  #define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_CLEAR_MASK (0x08000000)
    #define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_DISABLE (0b0)
    #define PERI1PLL_GATE_STAT_REG_PERI1_800M_GATE_STAT_ENABLE (0b1)
  #define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_OFFSET 26
  #define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_CLEAR_MASK (0x04000000)
    #define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_DISABLE (0b0)
    #define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_ALL_STAT_ENABLE (0b1)
  #define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_OFFSET 25
  #define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_CLEAR_MASK (0x02000000)
    #define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_DISABLE (0b0)
    #define PERI1PLL_GATE_STAT_REG_PERI1_600M_GATE_STAT_ENABLE (0b1)
  #define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_OFFSET 24
  #define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_CLEAR_MASK (0x01000000)
    #define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_DISABLE (0b0)
    #define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_ALL_STAT_ENABLE (0b1)
  #define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_OFFSET 23
  #define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_CLEAR_MASK (0x00800000)
    #define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_DISABLE (0b0)
    #define PERI1PLL_GATE_STAT_REG_PERI1_480M_GATE_STAT_ENABLE (0b1)
  #define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_OFFSET 22
  #define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_CLEAR_MASK (0x00400000)
    #define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_DISABLE (0b0)
    #define PERI1PLL_GATE_STAT_REG_PERI1_160M_GATE_STAT_ENABLE (0b1)
  #define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_OFFSET 21
  #define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_CLEAR_MASK (0x00200000)
    #define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_DISABLE (0b0)
    #define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_ALL_STAT_ENABLE (0b1)
  #define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_OFFSET 20
  #define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_CLEAR_MASK (0x00100000)
    #define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_DISABLE (0b0)
    #define PERI1PLL_GATE_STAT_REG_PERI1_300M_GATE_STAT_ENABLE (0b1)
  #define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_OFFSET 19
  #define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_CLEAR_MASK (0x00080000)
    #define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_DISABLE (0b0)
    #define PERI1PLL_GATE_STAT_REG_PERI1_150M_GATE_STAT_ENABLE (0b1)
  #define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_OFFSET 18
  #define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_CLEAR_MASK (0x00040000)
    #define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_DISABLE (0b0)
    #define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_ALL_STAT_ENABLE (0b1)
  #define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_OFFSET 17
  #define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_CLEAR_MASK (0x00020000)
    #define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_DISABLE (0b0)
    #define PERI1PLL_GATE_STAT_REG_PERI1_400M_GATE_STAT_ENABLE (0b1)
  #define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_OFFSET 16
  #define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_CLEAR_MASK (0x00010000)
    #define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_DISABLE (0b0)
    #define PERI1PLL_GATE_STAT_REG_PERI1_200M_GATE_STAT_ENABLE (0b1)

#define VIDEOPLL_GATE_STAT_REG 0x00001990 //VIDEOPLL Gate Status Register
  #define VIDEOPLL_GATE_STAT_REG_VIDEO3PLL3X_GATE_STAT_OFFSET 23
  #define VIDEOPLL_GATE_STAT_REG_VIDEO3PLL3X_GATE_STAT_CLEAR_MASK (0x00800000)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO3PLL3X_GATE_STAT_DISABLE (0b0)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO3PLL3X_GATE_STAT_ENABLE (0b1)
  #define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_OFFSET 22
  #define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_CLEAR_MASK (0x00400000)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_DISABLE (0b0)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL3X_GATE_STAT_ENABLE (0b1)
  #define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_OFFSET 21
  #define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_CLEAR_MASK (0x00200000)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_DISABLE (0b0)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL3X_GATE_STAT_ENABLE (0b1)
  #define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_OFFSET 20
  #define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_CLEAR_MASK (0x00100000)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_DISABLE (0b0)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL3X_GATE_STAT_ENABLE (0b1)
  #define VIDEOPLL_GATE_STAT_REG_VIDEO3PLL4X_GATE_STAT_OFFSET 19
  #define VIDEOPLL_GATE_STAT_REG_VIDEO3PLL4X_GATE_STAT_CLEAR_MASK (0x00080000)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO3PLL4X_GATE_STAT_DISABLE (0b0)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO3PLL4X_GATE_STAT_ENABLE (0b1)
  #define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_OFFSET 18
  #define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_CLEAR_MASK (0x00040000)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_DISABLE (0b0)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO2PLL4X_GATE_STAT_ENABLE (0b1)
  #define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_OFFSET 17
  #define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_CLEAR_MASK (0x00020000)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_DISABLE (0b0)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO1PLL4X_GATE_STAT_ENABLE (0b1)
  #define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_OFFSET 16
  #define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_CLEAR_MASK (0x00010000)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_DISABLE (0b0)
    #define VIDEOPLL_GATE_STAT_REG_VIDEO0PLL4X_GATE_STAT_ENABLE (0b1)

#define GPUPLL_GATE_STAT_REG 0x00001994 //GPUPLL Gate Status Register
  #define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_OFFSET 16
  #define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_CLEAR_MASK (0x00010000)
    #define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_DISABLE (0b0)
    #define GPUPLL_GATE_STAT_REG_GPU0PLL_GATE_STAT_ENABLE (0b1)

#define VEPLL_GATE_STAT_REG 0x00001998 //VEPLL Gate Status Register
  #define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_OFFSET 17
  #define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_CLEAR_MASK (0x00020000)
    #define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_DISABLE (0b0)
    #define VEPLL_GATE_STAT_REG_VE1PLL_GATE_STAT_ENABLE (0b1)
  #define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_OFFSET 16
  #define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_CLEAR_MASK (0x00010000)
    #define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_DISABLE (0b0)
    #define VEPLL_GATE_STAT_REG_VE0PLL_GATE_STAT_ENABLE (0b1)

#define AUDIOPLL_GATE_STAT_REG 0x0000199c //AUDIOPLL Gate Status Register
  #define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_OFFSET 16
  #define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_CLEAR_MASK (0x00010000)
    #define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_DISABLE (0b0)
    #define AUDIOPLL_GATE_STAT_REG_AUDIO0PLL4X_GATE_STAT_ENABLE (0b1)

#define NPUPLL_GATE_STAT_REG 0x000019a0 //NPUPLL Gate Status Register
  #define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_OFFSET 16
  #define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_CLEAR_MASK (0x00010000)
    #define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_DISABLE (0b0)
    #define NPUPLL_GATE_STAT_REG_NPUPLL_GATE_STAT_ENABLE (0b1)

#define DEPLL_GATE_STAT_REG 0x000019a8 //DEPLL Gate Status Register
  #define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_OFFSET 17
  #define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_CLEAR_MASK (0x00020000)
    #define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_DISABLE (0b0)
    #define DEPLL_GATE_STAT_REG_DEPLL3X_GATE_STAT_ENABLE (0b1)
  #define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_OFFSET 16
  #define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_CLEAR_MASK (0x00010000)
    #define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_DISABLE (0b0)
    #define DEPLL_GATE_STAT_REG_DEPLL4X_GATE_STAT_ENABLE (0b1)

#define CCIPLL_GATE_STAT_REG 0x000019b0 //CCIPLL Gate Status Register
  #define CCIPLL_GATE_STAT_REG_CCIPLL_GATE_STAT_OFFSET 16
  #define CCIPLL_GATE_STAT_REG_CCIPLL_GATE_STAT_CLEAR_MASK (0x00010000)
    #define CCIPLL_GATE_STAT_REG_CCIPLL_GATE_STAT_DISABLE (0b0)
    #define CCIPLL_GATE_STAT_REG_CCIPLL_GATE_STAT_ENABLE (0b1)

#define CLK24M_GATE_EN_REG 0x00001a00 //CLK24M Gate Enable register
  #define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET 3
  #define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK (0x00000008)
    #define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE (0b0)
    #define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE (0b1)

#define CM_VI_CFG_REG 0x00001b00 //CM VI Enable Configuration Register
  #define CM_VI_CFG_REG_CM_VI_STATUS_OFFSET 16
  #define CM_VI_CFG_REG_CM_VI_STATUS_CLEAR_MASK (0x00030000)
    #define CM_VI_CFG_REG_CM_VI_STATUS_POWER_OFF (0b01)
    #define CM_VI_CFG_REG_CM_VI_STATUS_POWER_ON (0b10)
  #define CM_VI_CFG_REG_CM_VI_MODULE_MODE_OFFSET 0
  #define CM_VI_CFG_REG_CM_VI_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_VI_CFG_REG_CM_VI_MODULE_MODE_DISABLE (0b0)
    #define CM_VI_CFG_REG_CM_VI_MODULE_MODE_ENABLE (0b1)

#define CM_DESYS_CFG_REG 0x00001b04 //CM DESYS Enable Configuration Register
  #define CM_DESYS_CFG_REG_CM_DESYS_STATUS_OFFSET 16
  #define CM_DESYS_CFG_REG_CM_DESYS_STATUS_CLEAR_MASK (0x00030000)
    #define CM_DESYS_CFG_REG_CM_DESYS_STATUS_POWER_OFF (0b01)
    #define CM_DESYS_CFG_REG_CM_DESYS_STATUS_POWER_ON (0b10)
  #define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_OFFSET 0
  #define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_DISABLE (0b0)
    #define CM_DESYS_CFG_REG_CM_DESYS_MODULE_MODE_ENABLE (0b1)

#define CM_DE_CFG_REG 0x00001b08 //CM DE Enable Configuration Register
  #define CM_DE_CFG_REG_CM_DE_STATUS_OFFSET 16
  #define CM_DE_CFG_REG_CM_DE_STATUS_CLEAR_MASK (0x00030000)
    #define CM_DE_CFG_REG_CM_DE_STATUS_POWER_OFF (0b01)
    #define CM_DE_CFG_REG_CM_DE_STATUS_POWER_ON (0b10)
  #define CM_DE_CFG_REG_CM_DE_MODULE_MODE_OFFSET 0
  #define CM_DE_CFG_REG_CM_DE_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_DE_CFG_REG_CM_DE_MODULE_MODE_DISABLE (0b0)
    #define CM_DE_CFG_REG_CM_DE_MODULE_MODE_ENABLE (0b1)

#define CM_DI_CFG_REG 0x00001b0c //CM DI Enable Configuration Register
  #define CM_DI_CFG_REG_CM_DI_STATUS_OFFSET 16
  #define CM_DI_CFG_REG_CM_DI_STATUS_CLEAR_MASK (0x00030000)
    #define CM_DI_CFG_REG_CM_DI_STATUS_POWER_OFF (0b01)
    #define CM_DI_CFG_REG_CM_DI_STATUS_POWER_ON (0b10)
  #define CM_DI_CFG_REG_CM_DI_MODULE_MODE_OFFSET 0
  #define CM_DI_CFG_REG_CM_DI_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_DI_CFG_REG_CM_DI_MODULE_MODE_DISABLE (0b0)
    #define CM_DI_CFG_REG_CM_DI_MODULE_MODE_ENABLE (0b1)

#define CM_VE_DEC_CFG_REG 0x00001b10 //CM VE_DEC Enable Configuration Register
  #define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_OFFSET 16
  #define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_CLEAR_MASK (0x00030000)
    #define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_POWER_OFF (0b01)
    #define CM_VE_DEC_CFG_REG_CM_VE_DEC_STATUS_POWER_ON (0b10)
  #define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_OFFSET 0
  #define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_DISABLE (0b0)
    #define CM_VE_DEC_CFG_REG_CM_VE_DEC_MODULE_MODE_ENABLE (0b1)

#define CM_VE_ENC_CFG_REG 0x00001b14 //CM VE_ENC Enable Configuration Register
  #define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_OFFSET 16
  #define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_CLEAR_MASK (0x00030000)
    #define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_POWER_OFF (0b01)
    #define CM_VE_ENC_CFG_REG_CM_VE_ENC_STATUS_POWER_ON (0b10)
  #define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_OFFSET 0
  #define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_DISABLE (0b0)
    #define CM_VE_ENC_CFG_REG_CM_VE_ENC_MODULE_MODE_ENABLE (0b1)

#define CM_VE_ENC1_CFG_REG 0x00001b18 //CM VE_ENC1 Enable Configuration Register
  #define CM_VE_ENC1_CFG_REG_CM_VE_ENC1_STATUS_OFFSET 16
  #define CM_VE_ENC1_CFG_REG_CM_VE_ENC1_STATUS_CLEAR_MASK (0x00030000)
    #define CM_VE_ENC1_CFG_REG_CM_VE_ENC1_STATUS_POWER_OFF (0b01)
    #define CM_VE_ENC1_CFG_REG_CM_VE_ENC1_STATUS_POWER_ON (0b10)
  #define CM_VE_ENC1_CFG_REG_CM_VE_ENC1_MODULE_MODE_OFFSET 0
  #define CM_VE_ENC1_CFG_REG_CM_VE_ENC1_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_VE_ENC1_CFG_REG_CM_VE_ENC1_MODULE_MODE_DISABLE (0b0)
    #define CM_VE_ENC1_CFG_REG_CM_VE_ENC1_MODULE_MODE_ENABLE (0b1)

#define CM_NPU_CFG_REG 0x00001b1c //CM NPU Enable Configuration Register
  #define CM_NPU_CFG_REG_CM_NPU_STATUS_OFFSET 16
  #define CM_NPU_CFG_REG_CM_NPU_STATUS_CLEAR_MASK (0x00030000)
    #define CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_OFF (0b01)
    #define CM_NPU_CFG_REG_CM_NPU_STATUS_POWER_ON (0b10)
  #define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_OFFSET 0
  #define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_DISABLE (0b0)
    #define CM_NPU_CFG_REG_CM_NPU_MODULE_MODE_ENABLE (0b1)

#define CM_AIPU_CFG_REG 0x00001b20 //CM AIPU Enable Configuration Register
  #define CM_AIPU_CFG_REG_CM_AIPU_STATUS_OFFSET 16
  #define CM_AIPU_CFG_REG_CM_AIPU_STATUS_CLEAR_MASK (0x00030000)
    #define CM_AIPU_CFG_REG_CM_AIPU_STATUS_POWER_OFF (0b01)
    #define CM_AIPU_CFG_REG_CM_AIPU_STATUS_POWER_ON (0b10)
  #define CM_AIPU_CFG_REG_CM_AIPU_MODULE_MODE_OFFSET 0
  #define CM_AIPU_CFG_REG_CM_AIPU_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_AIPU_CFG_REG_CM_AIPU_MODULE_MODE_DISABLE (0b0)
    #define CM_AIPU_CFG_REG_CM_AIPU_MODULE_MODE_ENABLE (0b1)

#define CM_GPU0_CFG_REG 0x00001b24 //CM GPU0 Enable Configuration Register
  #define CM_GPU0_CFG_REG_CM_GPU0_STATUS_OFFSET 16
  #define CM_GPU0_CFG_REG_CM_GPU0_STATUS_CLEAR_MASK (0x00030000)
    #define CM_GPU0_CFG_REG_CM_GPU0_STATUS_POWER_OFF (0b01)
    #define CM_GPU0_CFG_REG_CM_GPU0_STATUS_POWER_ON (0b10)
  #define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_OFFSET 0
  #define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_DISABLE (0b0)
    #define CM_GPU0_CFG_REG_CM_GPU0_MODULE_MODE_ENABLE (0b1)

#define CM_PCIE0_CFG_REG 0x00001b28 //CM PCIE0 Enable Configuration Register
  #define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_OFFSET 16
  #define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_CLEAR_MASK (0x00030000)
    #define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_POWER_OFF (0b01)
    #define CM_PCIE0_CFG_REG_CM_PCIE0_STATUS_POWER_ON (0b10)
  #define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_OFFSET 0
  #define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_DISABLE (0b0)
    #define CM_PCIE0_CFG_REG_CM_PCIE0_MODULE_MODE_ENABLE (0b1)

#define CM_PCIE1_CFG_REG 0x00001b2c //CM PCIE1 Enable Configuration Register
  #define CM_PCIE1_CFG_REG_CM_PCIE1_STATUS_OFFSET 16
  #define CM_PCIE1_CFG_REG_CM_PCIE1_STATUS_CLEAR_MASK (0x00030000)
    #define CM_PCIE1_CFG_REG_CM_PCIE1_STATUS_POWER_OFF (0b01)
    #define CM_PCIE1_CFG_REG_CM_PCIE1_STATUS_POWER_ON (0b10)
  #define CM_PCIE1_CFG_REG_CM_PCIE1_MODULE_MODE_OFFSET 0
  #define CM_PCIE1_CFG_REG_CM_PCIE1_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_PCIE1_CFG_REG_CM_PCIE1_MODULE_MODE_DISABLE (0b0)
    #define CM_PCIE1_CFG_REG_CM_PCIE1_MODULE_MODE_ENABLE (0b1)

#define CM_USB3_CFG_REG 0x00001b30 //CM USB3 Enable Configuration Register
  #define CM_USB3_CFG_REG_CM_USB3_STATUS_OFFSET 16
  #define CM_USB3_CFG_REG_CM_USB3_STATUS_CLEAR_MASK (0x00030000)
    #define CM_USB3_CFG_REG_CM_USB3_STATUS_POWER_OFF (0b01)
    #define CM_USB3_CFG_REG_CM_USB3_STATUS_POWER_ON (0b10)
  #define CM_USB3_CFG_REG_CM_USB3_MODULE_MODE_OFFSET 0
  #define CM_USB3_CFG_REG_CM_USB3_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_USB3_CFG_REG_CM_USB3_MODULE_MODE_DISABLE (0b0)
    #define CM_USB3_CFG_REG_CM_USB3_MODULE_MODE_ENABLE (0b1)

#define CM_VO_CFG_REG 0x00001b34 //CM VO Enable Configuration Register
  #define CM_VO_CFG_REG_CM_VO_STATUS_OFFSET 16
  #define CM_VO_CFG_REG_CM_VO_STATUS_CLEAR_MASK (0x00030000)
    #define CM_VO_CFG_REG_CM_VO_STATUS_POWER_OFF (0b01)
    #define CM_VO_CFG_REG_CM_VO_STATUS_POWER_ON (0b10)
  #define CM_VO_CFG_REG_CM_VO_MODULE_MODE_OFFSET 0
  #define CM_VO_CFG_REG_CM_VO_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_VO_CFG_REG_CM_VO_MODULE_MODE_DISABLE (0b0)
    #define CM_VO_CFG_REG_CM_VO_MODULE_MODE_ENABLE (0b1)

#define CM_VO1_CFG_REG 0x00001b38 //CM VO1 Enable Configuration Register
  #define CM_VO1_CFG_REG_CM_VO1_STATUS_OFFSET 16
  #define CM_VO1_CFG_REG_CM_VO1_STATUS_CLEAR_MASK (0x00030000)
    #define CM_VO1_CFG_REG_CM_VO1_STATUS_POWER_OFF (0b01)
    #define CM_VO1_CFG_REG_CM_VO1_STATUS_POWER_ON (0b10)
  #define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_OFFSET 0
  #define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_CLEAR_MASK (0x00000001)
    #define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_DISABLE (0b0)
    #define CM_VO1_CFG_REG_CM_VO1_MODULE_MODE_ENABLE (0b1)

#define CCMU_SEC_SWITCH_REG 0x00001f00 //CCMU Security Switch Register
  #define CCMU_SEC_SWITCH_REG_MBUS_SEC_OFFSET 2
  #define CCMU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK (0x00000004)
    #define CCMU_SEC_SWITCH_REG_MBUS_SEC_SECURE (0b0)
    #define CCMU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE (0b1)
  #define CCMU_SEC_SWITCH_REG_BUS_SEC_OFFSET 1
  #define CCMU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK (0x00000002)
    #define CCMU_SEC_SWITCH_REG_BUS_SEC_SECURE (0b0)
    #define CCMU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE (0b1)
  #define CCMU_SEC_SWITCH_REG_PLL_SEC_OFFSET 0
  #define CCMU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK (0x00000001)
    #define CCMU_SEC_SWITCH_REG_PLL_SEC_SECURE (0b0)
    #define CCMU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE (0b1)

#define SYSDAP_REQ_CTRL_REG 0x00001f10 //SYSDAP REQ Control Register
  #define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET 0
  #define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK (0x00000001)

#define PLL_CFG0_REG 0x00001f20 //PLL Configuration0 Register
  #define PLL_CFG0_REG_PLL_CONFIG0_OFFSET 0
  #define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK (0xffffffff)

#define PLL_CFG1_REG 0x00001f24 //PLL Configuration1 Register
  #define PLL_CFG1_REG_PLL_CONFIG1_OFFSET 0
  #define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK (0xffffffff)

#define PLL_CFG2_REG 0x00001f28 //PLL Configuration2 Register
  #define PLL_CFG2_REG_PLL_CONFIG2_OFFSET 0
  #define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK (0xffffffff)

#define PLL_LOCK_DBG_CTRL_REG 0x00001f2c //PLL Lock Debug Control Register
  #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET 31
  #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK (0x80000000)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE (0b0)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE (0b1)
  #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET 20
  #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK (0x07f00000)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_REFPLL (0b0000000)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL (0b0000001)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI0PLL (0b0000010)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERI1PLL (0b0000011)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_GPU0PLL (0b0000100)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL (0b0000101)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO1PLL (0b0000110)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO2PLL (0b0000111)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO3PLL (0b0001000)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VE0PLL (0b0001001)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VE1PLL (0b0001010)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO0PLL (0b0001011)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL (0b0001100)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DEPLL (0b0001101)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CCIPLL (0b0001110)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIO1PLL (0b0100000)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU0PLL (0b1000000)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU1PLL (0b1000001)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU2PLL (0b1000010)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU3PLL (0b1000011)
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPU4PLL (0b1000100)

#define CCMU_FAN_GATE_REG 0x00001f30 //CCMU FANOUT CLOCK GATE Register
  #define CCMU_FAN_GATE_REG_CLK25M_EN_OFFSET 3
  #define CCMU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK (0x00000008)
    #define CCMU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF (0b0)
    #define CCMU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON (0b1)
  #define CCMU_FAN_GATE_REG_CLK16M_EN_OFFSET 2
  #define CCMU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK (0x00000004)
    #define CCMU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF (0b0)
    #define CCMU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON (0b1)
  #define CCMU_FAN_GATE_REG_CLK12M_EN_OFFSET 1
  #define CCMU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK (0x00000002)
    #define CCMU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF (0b0)
    #define CCMU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON (0b1)
  #define CCMU_FAN_GATE_REG_CLK24M_EN_OFFSET 0
  #define CCMU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK (0x00000001)
    #define CCMU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF (0b0)
    #define CCMU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON (0b1)

#define CLK27M_FAN_REG 0x00001f34 //CLK27M FANOUT Register
  #define CLK27M_FAN_REG_CLK27M_EN_OFFSET 31
  #define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK (0x80000000)
    #define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF (0b0)
    #define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON (0b1)
  #define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET 24
  #define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK (0x03000000)
    #define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL4X (0b000)
    #define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL4X (0b001)
    #define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL4X (0b010)
    #define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO3PLL4X (0b011)
  #define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET 8
  #define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK (0x00001f00)
  #define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET 0
  #define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK (0x0000001f)

#define CLK_FAN_REG 0x00001f38 //CLK FANOUT Register
  #define CLK_FAN_REG_PCLK_DIV_EN_OFFSET 31
  #define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK (0x80000000)
    #define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF (0b0)
    #define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON (0b1)
  #define CLK_FAN_REG_PCLK_DIV1_OFFSET 5
  #define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK (0x000003e0)
  #define CLK_FAN_REG_PCLK_DIV_OFFSET 0
  #define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK (0x0000001f)

#define CCMU_FAN_REG 0x00001f3c //CCMU FANOUT Register
  #define CCMU_FAN_REG_CLK_FANOUT3_EN_OFFSET 24
  #define CCMU_FAN_REG_CLK_FANOUT3_EN_CLEAR_MASK (0x01000000)
    #define CCMU_FAN_REG_CLK_FANOUT3_EN_CLOCK_IS_OFF (0b0)
    #define CCMU_FAN_REG_CLK_FANOUT3_EN_CLOCK_IS_ON (0b1)
  #define CCMU_FAN_REG_CLK_FANOUT2_EN_OFFSET 23
  #define CCMU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK (0x00800000)
    #define CCMU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF (0b0)
    #define CCMU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON (0b1)
  #define CCMU_FAN_REG_CLK_FANOUT1_EN_OFFSET 22
  #define CCMU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK (0x00400000)
    #define CCMU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF (0b0)
    #define CCMU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON (0b1)
  #define CCMU_FAN_REG_CLK_FANOUT0_EN_OFFSET 21
  #define CCMU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK (0x00200000)
    #define CCMU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF (0b0)
    #define CCMU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON (0b1)
  #define CCMU_FAN_REG_CLK_FANOUT3_SEL_OFFSET 9
  #define CCMU_FAN_REG_CLK_FANOUT3_SEL_CLEAR_MASK (0x00000e00)
    #define CCMU_FAN_REG_CLK_FANOUT3_SEL_CLK32K_FANOUT_FROM_SYSRTC (0b000)
    #define CCMU_FAN_REG_CLK_FANOUT3_SEL_CLK12M_FROM_SYS_CLK24M_2 (0b001)
    #define CCMU_FAN_REG_CLK_FANOUT3_SEL_CLK16M_FROM_PERI0_160M_10 (0b010)
    #define CCMU_FAN_REG_CLK_FANOUT3_SEL_CLK24M_FROM_SYS_CLK24M (0b011)
    #define CCMU_FAN_REG_CLK_FANOUT3_SEL_CLK25M_FROM_PERI0_150M_6 (0b100)
    #define CCMU_FAN_REG_CLK_FANOUT3_SEL_CLK27M (0b101)
    #define CCMU_FAN_REG_CLK_FANOUT3_SEL_PCLK (0b110)
  #define CCMU_FAN_REG_CLK_FANOUT2_SEL_OFFSET 6
  #define CCMU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK (0x000001c0)
    #define CCMU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC (0b000)
    #define CCMU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_SYS_CLK24M_2 (0b001)
    #define CCMU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI0_160M_10 (0b010)
    #define CCMU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_SYS_CLK24M (0b011)
    #define CCMU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI0_150M_6 (0b100)
    #define CCMU_FAN_REG_CLK_FANOUT2_SEL_CLK27M (0b101)
    #define CCMU_FAN_REG_CLK_FANOUT2_SEL_PCLK (0b110)
  #define CCMU_FAN_REG_CLK_FANOUT1_SEL_OFFSET 3
  #define CCMU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK (0x00000038)
    #define CCMU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC (0b000)
    #define CCMU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_SYS_CLK24M_2 (0b001)
    #define CCMU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI0_160M_10 (0b010)
    #define CCMU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_SYS_CLK24M (0b011)
    #define CCMU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI0_150M_6 (0b100)
    #define CCMU_FAN_REG_CLK_FANOUT1_SEL_CLK27M (0b101)
    #define CCMU_FAN_REG_CLK_FANOUT1_SEL_PCLK (0b110)
  #define CCMU_FAN_REG_CLK_FANOUT0_SEL_OFFSET 0
  #define CCMU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK (0x00000007)
    #define CCMU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC (0b000)
    #define CCMU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_SYS_CLK24M_2 (0b001)
    #define CCMU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI0_160M_10 (0b010)
    #define CCMU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_SYS_CLK24M (0b011)
    #define CCMU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI0_150M_6 (0b100)
    #define CCMU_FAN_REG_CLK_FANOUT0_SEL_CLK27M (0b101)
    #define CCMU_FAN_REG_CLK_FANOUT0_SEL_PCLK (0b110)

#define CCMU_VERSION_REG 0x00001ff0 //CCMU Version Register
  #define CCMU_VERSION_REG_CCMU_MAIN_VERSION_OFFSET 16
  #define CCMU_VERSION_REG_CCMU_MAIN_VERSION_CLEAR_MASK (0xffff0000)
  #define CCMU_VERSION_REG_CCMU_SUB_VERSION_OFFSET 0
  #define CCMU_VERSION_REG_CCMU_SUB_VERSION_CLEAR_MASK (0x0000ffff)


struct CCMU_st {
	uint32_t pll_ref_ctrl_reg;//pll_ref control register
	uint32_t pll_ref_lock_ctrl_reg;//pll_ref lock control register
	uint32_t pad_until_0x0010[2];
	uint32_t pll_ref_bias_reg;//pll_ref bias register
	uint32_t pad_until_0x0020[3];
	uint32_t pll_ddr_ctrl_reg;//pll_ddr control register
	uint32_t pll_ddr_lock_ctrl_reg;//pll_ddr lock control register
	uint32_t pll_ddr_pat0_ctrl_reg;//pll_ddr pattern0 control register
	uint32_t pll_ddr_pat1_ctrl_reg;//pll_ddr pattern1 control register
	uint32_t pll_ddr_bias_reg;//pll_ddr bias register
	uint32_t pad_until_0x00a0[27];
	uint32_t pll_peri0_ctrl_reg;//pll_peri0 control register
	uint32_t pll_peri0_lock_ctrl_reg;//pll_peri0 lock control register
	uint32_t pll_peri0_pat0_ctrl_reg;//pll_peri0 pattern0 control register
	uint32_t pll_peri0_pat1_ctrl_reg;//pll_peri0 pattern1 control register
	uint32_t pll_peri0_bias_reg;//pll_peri0 bias register
	uint32_t pad_until_0x00c0[3];
	uint32_t pll_peri1_ctrl_reg;//pll_peri1 control register
	uint32_t pll_peri1_lock_ctrl_reg;//pll_peri1 lock control register
	uint32_t pll_peri1_pat0_ctrl_reg;//pll_peri1 pattern0 control register
	uint32_t pll_peri1_pat1_ctrl_reg;//pll_peri1 pattern1 control register
	uint32_t pll_peri1_bias_reg;//pll_peri1 bias register
	uint32_t pad_until_0x00e0[3];
	uint32_t pll_gpu0_ctrl_reg;//pll_gpu0 control register
	uint32_t pll_gpu0_lock_ctrl_reg;//pll_gpu0 lock control register
	uint32_t pll_gpu0_pat0_ctrl_reg;//pll_gpu0 pattern0 control register
	uint32_t pll_gpu0_pat1_ctrl_reg;//pll_gpu0 pattern1 control register
	uint32_t pll_gpu0_bias_reg;//pll_gpu0 bias register
	uint32_t pad_until_0x0120[11];
	uint32_t pll_video0_ctrl_reg;//pll_video0 control register
	uint32_t pll_video0_lock_ctrl_reg;//pll_video0 lock control register
	uint32_t pll_video0_pat0_ctrl_reg;//pll_video0 pattern0 control register
	uint32_t pll_video0_pat1_ctrl_reg;//pll_video0 pattern1 control register
	uint32_t pll_video0_bias_reg;//pll_video0 bias register
	uint32_t pad_until_0x0140[3];
	uint32_t pll_video1_ctrl_reg;//pll_video1 control register
	uint32_t pll_video1_lock_ctrl_reg;//pll_video1 lock control register
	uint32_t pll_video1_pat0_ctrl_reg;//pll_video1 pattern0 control register
	uint32_t pll_video1_pat1_ctrl_reg;//pll_video1 pattern1 control register
	uint32_t pll_video1_bias_reg;//pll_video1 bias register
	uint32_t pad_until_0x0160[3];
	uint32_t pll_video2_ctrl_reg;//pll_video2 control register
	uint32_t pll_video2_lock_ctrl_reg;//pll_video2 lock control register
	uint32_t pll_video2_pat0_ctrl_reg;//pll_video2 pattern0 control register
	uint32_t pll_video2_pat1_ctrl_reg;//pll_video2 pattern1 control register
	uint32_t pll_video2_bias_reg;//pll_video2 bias register
	uint32_t pad_until_0x0180[3];
	uint32_t pll_video3_ctrl_reg;//pll_video3 control register
	uint32_t pll_video3_lock_ctrl_reg;//pll_video3 lock control register
	uint32_t pll_video3_pat0_ctrl_reg;//pll_video3 pattern0 control register
	uint32_t pll_video3_pat1_ctrl_reg;//pll_video3 pattern1 control register
	uint32_t pll_video3_bias_reg;//pll_video3 bias register
	uint32_t pad_until_0x0220[35];
	uint32_t pll_ve0_ctrl_reg;//pll_ve0 control register
	uint32_t pll_ve0_lock_ctrl_reg;//pll_ve0 lock control register
	uint32_t pll_ve0_pat0_ctrl_reg;//pll_ve0 pattern0 control register
	uint32_t pll_ve0_pat1_ctrl_reg;//pll_ve0 pattern1 control register
	uint32_t pll_ve0_bias_reg;//pll_ve0 bias register
	uint32_t pad_until_0x0240[3];
	uint32_t pll_ve1_ctrl_reg;//pll_ve1 control register
	uint32_t pll_ve1_lock_ctrl_reg;//pll_ve1 lock control register
	uint32_t pll_ve1_pat0_ctrl_reg;//pll_ve1 pattern0 control register
	uint32_t pll_ve1_pat1_ctrl_reg;//pll_ve1 pattern1 control register
	uint32_t pll_ve1_bias_reg;//pll_ve1 bias register
	uint32_t pad_until_0x0260[3];
	uint32_t pll_audio0_ctrl_reg;//pll_audio0 control register
	uint32_t pll_audio0_lock_ctrl_reg;//pll_audio0 lock control register
	uint32_t pll_audio0_pat0_ctrl_reg;//pll_audio0 pattern0 control register
	uint32_t pll_audio0_pat1_ctrl_reg;//pll_audio0 pattern1 control register
	uint32_t pll_audio0_bias_reg;//pll_audio0 bias register
	uint32_t pad_until_0x02a0[11];
	uint32_t pll_npu_ctrl_reg;//pll_npu control register
	uint32_t pll_npu_lock_ctrl_reg;//pll_npu lock control register
	uint32_t pll_npu_pat0_ctrl_reg;//pll_npu pattern0 control register
	uint32_t pll_npu_pat1_ctrl_reg;//pll_npu pattern1 control register
	uint32_t pll_npu_bias_reg;//pll_npu bias register
	uint32_t pad_until_0x02e0[11];
	uint32_t pll_de_ctrl_reg;//pll_de control register
	uint32_t pll_de_lock_ctrl_reg;//pll_de lock control register
	uint32_t pll_de_pat0_ctrl_reg;//pll_de pattern0 control register
	uint32_t pll_de_pat1_ctrl_reg;//pll_de pattern1 control register
	uint32_t pll_de_bias_reg;//pll_de bias register
	uint32_t pad_until_0x0320[11];
	uint32_t pll_cci_ctrl_reg;//pll_cci control register
	uint32_t pll_cci_lock_ctrl_reg;//pll_cci lock control register
	uint32_t pll_cci_pat0_ctrl_reg;//pll_cci pattern0 control register
	uint32_t pll_cci_pat1_ctrl_reg;//pll_cci pattern1 control register
	uint32_t pll_cci_bias_reg;//pll_cci bias register
	uint32_t pad_until_0x0500[115];
	uint32_t ahb_clk_reg;//ahb clock register
	uint32_t pad_until_0x0510[3];
	uint32_t apb0_clk_reg;//apb0 clock register
	uint32_t pad_until_0x0518[1];
	uint32_t apb1_clk_reg;//apb1 clock register
	uint32_t pad_until_0x0538[7];
	uint32_t apb_uart_clk_reg;//apb_uart clock register
	uint32_t pad_until_0x0540[1];
	uint32_t trace_clk_reg;//trace clock register
	uint32_t pad_until_0x0548[1];
	uint32_t cci_clk_reg;//cci clock register
	uint32_t pad_until_0x0560[5];
	uint32_t gic_clk_reg;//gic clock register
	uint32_t pad_until_0x0580[7];
	uint32_t nsi_clk_reg;//nsi clock register
	uint32_t nsi_bgr_reg;//nsi bus gating reset register
	uint32_t mbus_clk_reg;//mbus clock register
	uint32_t smmu_bgr_reg;//smmu bus gating reset register
	uint32_t pad_until_0x0594[1];
	uint32_t msi_lite0_bgr_reg;//msi_lite0 bus gating reset register
	uint32_t pad_until_0x059c[1];
	uint32_t msi_lite1_bgr_reg;//msi_lite1 bus gating reset register
	uint32_t pad_until_0x05c0[8];
	uint32_t ahb_gate_en_reg;//ahb gate enable register
	uint32_t pad_until_0x05e0[7];
	uint32_t mbus_gate_en_reg;//mbus gate enable register
	uint32_t mbus_mat_clk_gating_reg;//mbus master clock gating register
	uint32_t pad_until_0x0704[71];
	uint32_t dma0_bgr_reg;//dma0 bus gating reset register
	uint32_t pad_until_0x070c[1];
	uint32_t dma1_bgr_reg;//dma1 bus gating reset register
	uint32_t pad_until_0x0724[5];
	uint32_t spinlock_bgr_reg;//spinlock bus gating reset register
	uint32_t pad_until_0x0744[7];
	uint32_t msgbox0_bgr_reg;//msgbox0 bus gating reset register
	uint32_t pad_until_0x074c[1];
	uint32_t msgbox1_bgr_reg;//msgbox1 bus gating reset register
	uint32_t pad_until_0x0754[1];
	uint32_t msgbox2_bgr_reg;//msgbox2 bus gating reset register
	uint32_t pad_until_0x0784[11];
	uint32_t pwm0_bgr_reg;//pwm0 bus gating reset register
	uint32_t pad_until_0x078c[1];
	uint32_t pwm1_bgr_reg;//pwm1 bus gating reset register
	uint32_t pad_until_0x07a4[5];
	uint32_t dbgsys_bgr_reg;//dbgsys bus gating reset register
	uint32_t pad_until_0x07ac[1];
	uint32_t sysdap_bgr_reg;//sysdap bus gating reset register
	uint32_t pad_until_0x0800[20];
	uint32_t timer0_clk0_clk_reg;//timer0_clk0 clock register
	uint32_t timer0_clk1_clk_reg;//timer0_clk1 clock register
	uint32_t timer0_clk2_clk_reg;//timer0_clk2 clock register
	uint32_t timer0_clk3_clk_reg;//timer0_clk3 clock register
	uint32_t timer0_clk4_clk_reg;//timer0_clk4 clock register
	uint32_t timer0_clk5_clk_reg;//timer0_clk5 clock register
	uint32_t timer0_clk6_clk_reg;//timer0_clk6 clock register
	uint32_t timer0_clk7_clk_reg;//timer0_clk7 clock register
	uint32_t timer0_clk8_clk_reg;//timer0_clk8 clock register
	uint32_t timer0_clk9_clk_reg;//timer0_clk9 clock register
	uint32_t pad_until_0x0850[10];
	uint32_t timer0_bgr_reg;//timer0 bus gating reset register
	uint32_t pad_until_0x0880[11];
	uint32_t timer1_clk0_clk_reg;//timer1_clk0 clock register
	uint32_t timer1_clk1_clk_reg;//timer1_clk1 clock register
	uint32_t timer1_clk2_clk_reg;//timer1_clk2 clock register
	uint32_t timer1_clk3_clk_reg;//timer1_clk3 clock register
	uint32_t timer1_clk4_clk_reg;//timer1_clk4 clock register
	uint32_t timer1_clk5_clk_reg;//timer1_clk5 clock register
	uint32_t pad_until_0x08c0[10];
	uint32_t timer1_bgr_reg;//timer1 bus gating reset register
	uint32_t pad_until_0x0a00[79];
	uint32_t de0_clk_reg;//de0 clock register
	uint32_t de0_bgr_reg;//de0 bus gating reset register
	uint32_t de1_clk_reg;//de1 clock register
	uint32_t de1_bgr_reg;//de1 bus gating reset register
	uint32_t pad_until_0x0a20[4];
	uint32_t di_clk_reg;//di clock register
	uint32_t di_bgr_reg;//di bus gating reset register
	uint32_t pad_until_0x0a40[6];
	uint32_t g2d_clk_reg;//g2d clock register
	uint32_t g2d_bgr_reg;//g2d bus gating reset register
	uint32_t pad_until_0x0a74[11];
	uint32_t de_sys_bgr_reg;//de_sys bus gating reset register
	uint32_t pad_until_0x0a80[2];
	uint32_t ve_enc0_clk_reg;//ve_enc0 clock register
	uint32_t ve_enc1_clk_reg;//ve_enc1 clock register
	uint32_t ve_dec_clk_reg;//ve_dec clock register
	uint32_t ve_bgr_reg;//ve bus gating reset register
	uint32_t pad_until_0x0ac0[12];
	uint32_t ce_clk_reg;//ce clock register
	uint32_t ce_bgr_reg;//ce bus gating reset register
	uint32_t pad_until_0x0b00[14];
	uint32_t npu_clk_reg;//npu clock register
	uint32_t npu_bgr_reg;//npu bus gating reset register
	uint32_t aipu_clk_reg;//aipu clock register
	uint32_t aipu_bgr_reg;//aipu bus gating reset register
	uint32_t pad_until_0x0b20[4];
	uint32_t gpu0_clk_reg;//gpu0 clock register
	uint32_t gpu0_gating_reg;//gpu0 gating reset configuration register
	uint32_t pad_until_0x0b40[6];
	uint32_t dsp_clk_reg;//dsp clock register
	uint32_t pad_until_0x0c00[47];
	uint32_t dram0_clk_reg;//dram0 clock register
	uint32_t pad_until_0x0c0c[2];
	uint32_t dram_bgr_reg;//dram bus gating reset register
	uint32_t pad_until_0x0c80[28];
	uint32_t nand0_clk0_clk_reg;//nand0 clk0 clock register
	uint32_t nand0_clk1_clk_reg;//nand0 clk1 clock register
	uint32_t pad_until_0x0c8c[1];
	uint32_t nand_bgr_reg;//nand bus gating reset register
	uint32_t pad_until_0x0d00[28];
	uint32_t smhc0_clk_reg;//smhc0 clock register
	uint32_t smhc0_24m_clk_reg;//smhc0_24m clock register
	uint32_t pad_until_0x0d0c[1];
	uint32_t smhc0_bgr_reg;//smhc0 bus gating reset register
	uint32_t smhc1_clk_reg;//smhc1 clock register
	uint32_t pad_until_0x0d1c[2];
	uint32_t smhc1_bgr_reg;//smhc1 bus gating reset register
	uint32_t smhc2_clk_reg;//smhc2 clock register
	uint32_t smhc2_24m_clk_reg;//smhc2_24m clock register
	uint32_t pad_until_0x0d2c[1];
	uint32_t smhc2_bgr_reg;//smhc2 bus gating reset register
	uint32_t smhc3_clk_reg;//smhc3 clock register
	uint32_t smhc3_24m_clk_reg;//smhc3_24m clock register
	uint32_t pad_until_0x0d3c[1];
	uint32_t smhc3_bgr_reg;//smhc3 bus gating reset register
	uint32_t pad_until_0x0d80[16];
	uint32_t ufs_axi_clk_reg;//ufs_axi clock register
	uint32_t pad_until_0x0d8c[2];
	uint32_t ufs_bgr_reg;//ufs bus gating reset register
	uint32_t pad_until_0x0e00[28];
	uint32_t uart0_bgr_reg;//uart0 bus gating reset register
	uint32_t uart1_bgr_reg;//uart1 bus gating reset register
	uint32_t uart2_bgr_reg;//uart2 bus gating reset register
	uint32_t uart3_bgr_reg;//uart3 bus gating reset register
	uint32_t uart4_bgr_reg;//uart4 bus gating reset register
	uint32_t uart5_bgr_reg;//uart5 bus gating reset register
	uint32_t uart6_bgr_reg;//uart6 bus gating reset register
	uint32_t uart7_bgr_reg;//uart7 bus gating reset register
	uint32_t uart8_bgr_reg;//uart8 bus gating reset register
	uint32_t pad_until_0x0e80[23];
	uint32_t twi0_bgr_reg;//twi0 bus gating reset register
	uint32_t twi1_bgr_reg;//twi1 bus gating reset register
	uint32_t twi2_bgr_reg;//twi2 bus gating reset register
	uint32_t twi3_bgr_reg;//twi3 bus gating reset register
	uint32_t twi4_bgr_reg;//twi4 bus gating reset register
	uint32_t twi5_bgr_reg;//twi5 bus gating reset register
	uint32_t twi6_bgr_reg;//twi6 bus gating reset register
	uint32_t twi7_bgr_reg;//twi7 bus gating reset register
	uint32_t twi8_bgr_reg;//twi8 bus gating reset register
	uint32_t pad_until_0x0f00[23];
	uint32_t spi0_clk_reg;//spi0 clock register
	uint32_t spi0_bgr_reg;//spi0 bus gating reset register
	uint32_t spi1_clk_reg;//spi1 clock register
	uint32_t spi1_bgr_reg;//spi1 bus gating reset register
	uint32_t spi2_clk_reg;//spi2 clock register
	uint32_t spi2_bgr_reg;//spi2 bus gating reset register
	uint32_t spif_clk_reg;//spif clock register
	uint32_t spif_bgr_reg;//spif bus gating reset register
	uint32_t pad_until_0x0f80[24];
	uint32_t res[6];
	uint32_t pad_until_0x0fbc[9];
	uint32_t can_sys_bgr_reg;//can_sys bus gating reset register
	uint32_t gpadc0_24m_clk_reg;//gpadc0_24m clock register
	uint32_t gpadc0_bgr_reg;//gpadc0 bus gating reset register
	uint32_t gpadc1_24m_clk_reg;//gpadc1_24m clock register
	uint32_t gpadc1_bgr_reg;//gpadc1 bus gating reset register
	uint32_t pad_until_0x0fe4[5];
	uint32_t ths0_bgr_reg;//ths0 bus gating reset register
	uint32_t pad_until_0x1000[6];
	uint32_t irrx_clk_reg;//irrx clock register
	uint32_t irrx_bgr_reg;//irrx bus gating reset register
	uint32_t irtx_clk_reg;//irtx clock register
	uint32_t irtx_bgr_reg;//irtx bus gating reset register
	uint32_t pad_until_0x1024[5];
	uint32_t lradc_bgr_reg;//lradc bus gating reset register
	uint32_t pad_until_0x1040[6];
	uint32_t lbc_clk_reg;//lbc clock register
	uint32_t lbc_bgr_reg;//lbc bus gating reset register
	uint32_t pad_until_0x1210[114];
	uint32_t i2spcm1_clk_reg;//i2spcm1 clock register
	uint32_t pad_until_0x121c[2];
	uint32_t i2spcm1_bgr_reg;//i2spcm1 bus gating reset register
	uint32_t i2spcm2_clk_reg;//i2spcm2 clock register
	uint32_t i2spcm2_asrc_clk_reg;//i2spcm2_asrc clock register
	uint32_t pad_until_0x122c[1];
	uint32_t i2spcm2_bgr_reg;//i2spcm2 bus gating reset register
	uint32_t i2spcm3_clk_reg;//i2spcm3 clock register
	uint32_t pad_until_0x123c[2];
	uint32_t i2spcm3_bgr_reg;//i2spcm3 bus gating reset register
	uint32_t i2spcm4_clk_reg;//i2spcm4 clock register
	uint32_t pad_until_0x124c[2];
	uint32_t i2spcm4_bgr_reg;//i2spcm4 bus gating reset register
	uint32_t i2spcm5_clk_reg;//i2spcm5 clock register
	uint32_t pad_until_0x125c[2];
	uint32_t i2spcm5_bgr_reg;//i2spcm5 bus gating reset register
	uint32_t pad_until_0x1280[8];
	uint32_t spdif_tx_clk_reg;//spdif tx clock register
	uint32_t spdif_rx_clk_reg;//spdif rx clock register
	uint32_t pad_until_0x128c[1];
	uint32_t spdif_bgr_reg;//spdif bus gating reset register
	uint32_t pad_until_0x1300[28];
	uint32_t usb2_host0_clk_reg;//usb2_host0 clock register
	uint32_t usb2_host0_bgr_reg;//usb2_host0 bus gating reset register
	uint32_t usb2_host1_clk_reg;//usb2_host1 clock register
	uint32_t usb2_host1_bgr_reg;//usb2_host1 bus gating reset register
	uint32_t usb2_host2_clk_reg;//usb2_host2 clock register
	uint32_t usb2_host2_bgr_reg;//usb2_host2 bus gating reset register
	uint32_t pad_until_0x1340[10];
	uint32_t usb2_ref_clk_reg;//usb2_ref clock register
	uint32_t pad_until_0x1348[1];
	uint32_t usb3_usb2_ref_clk_reg;//usb3_usb2_ref clock register
	uint32_t pad_until_0x1350[1];
	uint32_t usb3_suspend_clk_reg;//usb3_suspend clock register
	uint32_t usb3_bgr_reg;//usb3 bus gating reset register
	uint32_t pad_until_0x1380[10];
	uint32_t pcie0_aux_clk_reg;//pcie0_aux clock register
	uint32_t pad_until_0x138c[2];
	uint32_t pcie0_bgr_reg;//pcie0 bus gating reset register
	uint32_t pcie1_aux_clk_reg;//pcie1_aux clock register
	uint32_t pad_until_0x139c[2];
	uint32_t pcie1_bgr_reg;//pcie1 bus gating reset register
	uint32_t pad_until_0x13c4[9];
	uint32_t serdes_bgr_reg;//serdes bus gating reset register
	uint32_t pad_until_0x1400[14];
	uint32_t gmac_ptp_clk_reg;//gmac_ptp clock register
	uint32_t pad_until_0x1410[3];
	uint32_t gmac0_phy_clk_reg;//gmac0_phy clock register
	uint32_t pad_until_0x141c[2];
	uint32_t gmac0_bgr_reg;//gmac0 bus gating reset register
	uint32_t gmac1_phy_clk_reg;//gmac1_phy clock register
	uint32_t pad_until_0x142c[2];
	uint32_t gmac1_bgr_reg;//gmac1 bus gating reset register
	uint32_t pad_until_0x1500[52];
	uint32_t vo0_tconlcd0_clk_reg;//vo0_tconlcd0 clock register
	uint32_t vo0_tconlcd0_bgr_reg;//vo0_tconlcd0 bus gating reset register
	uint32_t vo0_tconlcd1_clk_reg;//vo0_tconlcd1 clock register
	uint32_t vo0_tconlcd1_bgr_reg;//vo0_tconlcd1 bus gating reset register
	uint32_t vo0_tconlcd2_clk_reg;//vo0_tconlcd2 clock register
	uint32_t vo0_tconlcd2_bgr_reg;//vo0_tconlcd2 bus gating reset register
	uint32_t vo0_tconlcd3_clk_reg;//vo0_tconlcd3 clock register
	uint32_t vo0_tconlcd3_bgr_reg;//vo0_tconlcd3 bus gating reset register
	uint32_t pad_until_0x1544[9];
	uint32_t lvds0_bgr_reg;//lvds0 bus gating reset register
	uint32_t pad_until_0x154c[1];
	uint32_t lvds1_bgr_reg;//lvds1 bus gating reset register
	uint32_t pad_until_0x1554[1];
	uint32_t lvds2_bgr_reg;//lvds2 bus gating reset register
	uint32_t pad_until_0x1580[10];
	uint32_t dsi0_clk_reg;//dsi0 clock register
	uint32_t dsi0_bgr_reg;//dsi0 bus gating reset register
	uint32_t dsi1_clk_reg;//dsi1 clock register
	uint32_t dsi1_bgr_reg;//dsi1 bus gating reset register
	uint32_t pad_until_0x15c0[12];
	uint32_t combphy0_clk_reg;//combphy0 clock register
	uint32_t combphy1_clk_reg;//combphy1 clock register
	uint32_t pad_until_0x1600[14];
	uint32_t tcontv0_clk_reg;//tcontv0 clock register
	uint32_t tcontv0_bgr_reg;//tcontv0 bus gating reset register
	uint32_t pad_until_0x160c[1];
	uint32_t tcontv1_bgr_reg;//tcontv1 bus gating reset register
	uint32_t pad_until_0x1614[1];
	uint32_t tcontv2_bgr_reg;//tcontv2 bus gating reset register
	uint32_t pad_until_0x1640[10];
	uint32_t edp_clk0_clk_reg;//edp_clk0 clock register
	uint32_t edp_clk1_clk_reg;//edp_clk1 clock register
	uint32_t pad_until_0x164c[1];
	uint32_t edp_bgr_reg;//edp bus gating reset register
	uint32_t pad_until_0x1680[12];
	uint32_t hdmi_ref_clk_reg;//hdmi ref clock register
	uint32_t hdmi_pre_clk_reg;//hdmi pre clock register
	uint32_t pad_until_0x168c[1];
	uint32_t hdmi_bgr_reg;//hdmi bus gating reset register
	uint32_t pad_until_0x16c4[13];
	uint32_t dpss_top0_bgr_reg;//dpss_top0 bus gating reset register
	uint32_t pad_until_0x16cc[1];
	uint32_t dpss_top1_bgr_reg;//dpss_top1 bus gating reset register
	uint32_t pad_until_0x16e4[5];
	uint32_t video_out0_bgr_reg;//video_out0 bus gating reset register
	uint32_t pad_until_0x16ec[1];
	uint32_t video_out1_bgr_reg;//video_out1 bus gating reset register
	uint32_t pad_until_0x1700[4];
	uint32_t ledc_clk_reg;//ledc clock register
	uint32_t ledc_bgr_reg;//ledc bus gating reset register
	uint32_t pad_until_0x1800[62];
	uint32_t csi_master0_clk_reg;//csi master0 clock register
	uint32_t csi_master1_clk_reg;//csi master1 clock register
	uint32_t csi_master2_clk_reg;//csi master2 clock register
	uint32_t csi_master3_clk_reg;//csi master3 clock register
	uint32_t pad_until_0x1840[12];
	uint32_t csi_clk_reg;//csi clock register
	uint32_t csi_bgr_reg;//csi bus gating reset register
	uint32_t pad_until_0x1860[6];
	uint32_t isp_clk_reg;//isp clock register
	uint32_t pad_until_0x1884[8];
	uint32_t video_in_bgr_reg;//video_in bus gating reset register
	uint32_t pad_until_0x1904[31];
	uint32_t ddrpll_gate_en_reg;//ddrpll gate enable register
	uint32_t peri0pll_gate_en_reg;//peri0pll gate enable register
	uint32_t peri1pll_gate_en_reg;//peri1pll gate enable register
	uint32_t videopll_gate_en_reg;//videopll gate enable register
	uint32_t gpupll_gate_en_reg;//gpupll gate enable register
	uint32_t vepll_gate_en_reg;//vepll gate enable register
	uint32_t audiopll_gate_en_reg;//audiopll gate enable register
	uint32_t npupll_gate_en_reg;//npupll gate enable register
	uint32_t pad_until_0x1928[1];
	uint32_t depll_gate_en_reg;//depll gate enable register
	uint32_t pad_until_0x1930[1];
	uint32_t ccipll_gate_en_reg;//ccipll gate enable register
	uint32_t pad_until_0x1984[20];
	uint32_t ddrpll_gate_stat_reg;//ddrpll gate status register
	uint32_t peri0pll_gate_stat_reg;//peri0pll gate status register
	uint32_t peri1pll_gate_stat_reg;//peri1pll gate status register
	uint32_t videopll_gate_stat_reg;//videopll gate status register
	uint32_t gpupll_gate_stat_reg;//gpupll gate status register
	uint32_t vepll_gate_stat_reg;//vepll gate status register
	uint32_t audiopll_gate_stat_reg;//audiopll gate status register
	uint32_t npupll_gate_stat_reg;//npupll gate status register
	uint32_t pad_until_0x19a8[1];
	uint32_t depll_gate_stat_reg;//depll gate status register
	uint32_t pad_until_0x19b0[1];
	uint32_t ccipll_gate_stat_reg;//ccipll gate status register
	uint32_t pad_until_0x1a00[19];
	uint32_t clk24m_gate_en_reg;//clk24m gate enable register
	uint32_t pad_until_0x1b00[63];
	uint32_t cm_vi_cfg_reg;//cm vi enable configuration register
	uint32_t cm_desys_cfg_reg;//cm desys enable configuration register
	uint32_t cm_de_cfg_reg;//cm de enable configuration register
	uint32_t cm_di_cfg_reg;//cm di enable configuration register
	uint32_t cm_ve_dec_cfg_reg;//cm ve_dec enable configuration register
	uint32_t cm_ve_enc_cfg_reg;//cm ve_enc enable configuration register
	uint32_t cm_ve_enc1_cfg_reg;//cm ve_enc1 enable configuration register
	uint32_t cm_npu_cfg_reg;//cm npu enable configuration register
	uint32_t cm_aipu_cfg_reg;//cm aipu enable configuration register
	uint32_t cm_gpu0_cfg_reg;//cm gpu0 enable configuration register
	uint32_t cm_pcie0_cfg_reg;//cm pcie0 enable configuration register
	uint32_t cm_pcie1_cfg_reg;//cm pcie1 enable configuration register
	uint32_t cm_usb3_cfg_reg;//cm usb3 enable configuration register
	uint32_t cm_vo_cfg_reg;//cm vo enable configuration register
	uint32_t cm_vo1_cfg_reg;//cm vo1 enable configuration register
	uint32_t pad_until_0x1f00[241];
	uint32_t ccmu_sec_switch_reg;//ccmu security switch register
	uint32_t pad_until_0x1f10[3];
	uint32_t sysdap_req_ctrl_reg;//sysdap req control register
	uint32_t pad_until_0x1f20[3];
	uint32_t pll_cfg0_reg;//pll configuration0 register
	uint32_t pll_cfg1_reg;//pll configuration1 register
	uint32_t pll_cfg2_reg;//pll configuration2 register
	uint32_t pll_lock_dbg_ctrl_reg;//pll lock debug control register
	uint32_t ccmu_fan_gate_reg;//ccmu fanout clock gate register
	uint32_t clk27m_fan_reg;//clk27m fanout register
	uint32_t clk_fan_reg;//clk fanout register
	uint32_t ccmu_fan_reg;//ccmu fanout register
	uint32_t pad_until_0x1ff0[44];
	uint32_t ccmu_version_reg;//ccmu version register
};